358 lines
8.7 KiB
C
358 lines
8.7 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
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*
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* Derived from drivers/mtd/nand/toto.c (removed in v2.6.28)
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* Copyright (c) 2003 Texas Instruments
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* Copyright (c) 2002 Thomas Gleixner <tgxl@linutronix.de>
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*
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* Converted to platform driver by Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
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* Partially stolen from plat_nand.c
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*
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* Overview:
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* This is a device driver for the NAND flash device found on the
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* Amstrad E3 (Delta).
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*/
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <linux/sizes.h>
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/*
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* MTD structure for E3 (Delta)
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*/
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struct ams_delta_nand {
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struct nand_controller base;
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struct nand_chip nand_chip;
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struct gpio_desc *gpiod_rdy;
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struct gpio_desc *gpiod_nce;
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struct gpio_desc *gpiod_nre;
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struct gpio_desc *gpiod_nwp;
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struct gpio_desc *gpiod_nwe;
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struct gpio_desc *gpiod_ale;
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struct gpio_desc *gpiod_cle;
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struct gpio_descs *data_gpiods;
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bool data_in;
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};
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/*
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* Define partitions for flash devices
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*/
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static const struct mtd_partition partition_info[] = {
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{ .name = "Kernel",
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.offset = 0,
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.size = 3 * SZ_1M + SZ_512K },
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{ .name = "u-boot",
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.offset = 3 * SZ_1M + SZ_512K,
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.size = SZ_256K },
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{ .name = "u-boot params",
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.offset = 3 * SZ_1M + SZ_512K + SZ_256K,
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.size = SZ_256K },
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{ .name = "Amstrad LDR",
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.offset = 4 * SZ_1M,
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.size = SZ_256K },
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{ .name = "File system",
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.offset = 4 * SZ_1M + 1 * SZ_256K,
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.size = 27 * SZ_1M },
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{ .name = "PBL reserved",
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.offset = 32 * SZ_1M - 3 * SZ_256K,
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.size = 3 * SZ_256K },
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};
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static void ams_delta_write_commit(struct ams_delta_nand *priv)
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{
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gpiod_set_value(priv->gpiod_nwe, 0);
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ndelay(40);
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gpiod_set_value(priv->gpiod_nwe, 1);
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}
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static void ams_delta_io_write(struct ams_delta_nand *priv, u8 byte)
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{
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struct gpio_descs *data_gpiods = priv->data_gpiods;
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DECLARE_BITMAP(values, BITS_PER_TYPE(byte)) = { byte, };
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gpiod_set_raw_array_value(data_gpiods->ndescs, data_gpiods->desc,
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data_gpiods->info, values);
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ams_delta_write_commit(priv);
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}
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static void ams_delta_dir_output(struct ams_delta_nand *priv, u8 byte)
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{
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struct gpio_descs *data_gpiods = priv->data_gpiods;
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DECLARE_BITMAP(values, BITS_PER_TYPE(byte)) = { byte, };
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int i;
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for (i = 0; i < data_gpiods->ndescs; i++)
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gpiod_direction_output_raw(data_gpiods->desc[i],
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test_bit(i, values));
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ams_delta_write_commit(priv);
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priv->data_in = false;
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}
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static u8 ams_delta_io_read(struct ams_delta_nand *priv)
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{
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u8 res;
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struct gpio_descs *data_gpiods = priv->data_gpiods;
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DECLARE_BITMAP(values, BITS_PER_TYPE(res)) = { 0, };
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gpiod_set_value(priv->gpiod_nre, 0);
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ndelay(40);
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gpiod_get_raw_array_value(data_gpiods->ndescs, data_gpiods->desc,
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data_gpiods->info, values);
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gpiod_set_value(priv->gpiod_nre, 1);
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res = values[0];
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return res;
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}
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static void ams_delta_dir_input(struct ams_delta_nand *priv)
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{
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struct gpio_descs *data_gpiods = priv->data_gpiods;
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int i;
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for (i = 0; i < data_gpiods->ndescs; i++)
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gpiod_direction_input(data_gpiods->desc[i]);
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priv->data_in = true;
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}
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static void ams_delta_write_buf(struct ams_delta_nand *priv, const u8 *buf,
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int len)
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{
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int i = 0;
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if (len > 0 && priv->data_in)
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ams_delta_dir_output(priv, buf[i++]);
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while (i < len)
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ams_delta_io_write(priv, buf[i++]);
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}
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static void ams_delta_read_buf(struct ams_delta_nand *priv, u8 *buf, int len)
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{
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int i;
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if (!priv->data_in)
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ams_delta_dir_input(priv);
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for (i = 0; i < len; i++)
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buf[i] = ams_delta_io_read(priv);
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}
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static void ams_delta_ctrl_cs(struct ams_delta_nand *priv, bool assert)
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{
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gpiod_set_value(priv->gpiod_nce, assert ? 0 : 1);
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}
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static int ams_delta_exec_op(struct nand_chip *this,
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const struct nand_operation *op, bool check_only)
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{
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struct ams_delta_nand *priv = nand_get_controller_data(this);
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const struct nand_op_instr *instr;
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int ret = 0;
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if (check_only)
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return 0;
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ams_delta_ctrl_cs(priv, 1);
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for (instr = op->instrs; instr < op->instrs + op->ninstrs; instr++) {
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switch (instr->type) {
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case NAND_OP_CMD_INSTR:
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gpiod_set_value(priv->gpiod_cle, 1);
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ams_delta_write_buf(priv, &instr->ctx.cmd.opcode, 1);
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gpiod_set_value(priv->gpiod_cle, 0);
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break;
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case NAND_OP_ADDR_INSTR:
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gpiod_set_value(priv->gpiod_ale, 1);
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ams_delta_write_buf(priv, instr->ctx.addr.addrs,
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instr->ctx.addr.naddrs);
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gpiod_set_value(priv->gpiod_ale, 0);
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break;
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case NAND_OP_DATA_IN_INSTR:
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ams_delta_read_buf(priv, instr->ctx.data.buf.in,
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instr->ctx.data.len);
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break;
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case NAND_OP_DATA_OUT_INSTR:
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ams_delta_write_buf(priv, instr->ctx.data.buf.out,
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instr->ctx.data.len);
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break;
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case NAND_OP_WAITRDY_INSTR:
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ret = priv->gpiod_rdy ?
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nand_gpio_waitrdy(this, priv->gpiod_rdy,
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instr->ctx.waitrdy.timeout_ms) :
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nand_soft_waitrdy(this,
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instr->ctx.waitrdy.timeout_ms);
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break;
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}
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if (ret)
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break;
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}
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ams_delta_ctrl_cs(priv, 0);
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return ret;
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}
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static const struct nand_controller_ops ams_delta_ops = {
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.exec_op = ams_delta_exec_op,
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};
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/*
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* Main initialization routine
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*/
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static int ams_delta_init(struct platform_device *pdev)
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{
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struct ams_delta_nand *priv;
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struct nand_chip *this;
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struct mtd_info *mtd;
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struct gpio_descs *data_gpiods;
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int err = 0;
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/* Allocate memory for MTD device structure and private data */
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priv = devm_kzalloc(&pdev->dev, sizeof(struct ams_delta_nand),
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GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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this = &priv->nand_chip;
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mtd = nand_to_mtd(this);
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mtd->dev.parent = &pdev->dev;
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nand_set_controller_data(this, priv);
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priv->gpiod_rdy = devm_gpiod_get_optional(&pdev->dev, "rdy", GPIOD_IN);
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if (IS_ERR(priv->gpiod_rdy)) {
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err = PTR_ERR(priv->gpiod_rdy);
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dev_warn(&pdev->dev, "RDY GPIO request failed (%d)\n", err);
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return err;
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}
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this->ecc.mode = NAND_ECC_SOFT;
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this->ecc.algo = NAND_ECC_HAMMING;
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platform_set_drvdata(pdev, priv);
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/* Set chip enabled, but */
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priv->gpiod_nwp = devm_gpiod_get(&pdev->dev, "nwp", GPIOD_OUT_HIGH);
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if (IS_ERR(priv->gpiod_nwp)) {
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err = PTR_ERR(priv->gpiod_nwp);
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dev_err(&pdev->dev, "NWP GPIO request failed (%d)\n", err);
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return err;
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}
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priv->gpiod_nce = devm_gpiod_get(&pdev->dev, "nce", GPIOD_OUT_HIGH);
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if (IS_ERR(priv->gpiod_nce)) {
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err = PTR_ERR(priv->gpiod_nce);
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dev_err(&pdev->dev, "NCE GPIO request failed (%d)\n", err);
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return err;
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}
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priv->gpiod_nre = devm_gpiod_get(&pdev->dev, "nre", GPIOD_OUT_HIGH);
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if (IS_ERR(priv->gpiod_nre)) {
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err = PTR_ERR(priv->gpiod_nre);
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dev_err(&pdev->dev, "NRE GPIO request failed (%d)\n", err);
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return err;
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}
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priv->gpiod_nwe = devm_gpiod_get(&pdev->dev, "nwe", GPIOD_OUT_HIGH);
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if (IS_ERR(priv->gpiod_nwe)) {
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err = PTR_ERR(priv->gpiod_nwe);
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dev_err(&pdev->dev, "NWE GPIO request failed (%d)\n", err);
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return err;
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}
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priv->gpiod_ale = devm_gpiod_get(&pdev->dev, "ale", GPIOD_OUT_LOW);
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if (IS_ERR(priv->gpiod_ale)) {
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err = PTR_ERR(priv->gpiod_ale);
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dev_err(&pdev->dev, "ALE GPIO request failed (%d)\n", err);
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return err;
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}
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priv->gpiod_cle = devm_gpiod_get(&pdev->dev, "cle", GPIOD_OUT_LOW);
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if (IS_ERR(priv->gpiod_cle)) {
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err = PTR_ERR(priv->gpiod_cle);
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dev_err(&pdev->dev, "CLE GPIO request failed (%d)\n", err);
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return err;
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}
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/* Request array of data pins, initialize them as input */
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data_gpiods = devm_gpiod_get_array(&pdev->dev, "data", GPIOD_IN);
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if (IS_ERR(data_gpiods)) {
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err = PTR_ERR(data_gpiods);
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dev_err(&pdev->dev, "data GPIO request failed: %d\n", err);
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return err;
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}
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priv->data_gpiods = data_gpiods;
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priv->data_in = true;
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/* Initialize the NAND controller object embedded in ams_delta_nand. */
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priv->base.ops = &ams_delta_ops;
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nand_controller_init(&priv->base);
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this->controller = &priv->base;
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/* Scan to find existence of the device */
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err = nand_scan(this, 1);
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if (err)
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return err;
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/* Register the partitions */
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err = mtd_device_register(mtd, partition_info,
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ARRAY_SIZE(partition_info));
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if (err)
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goto err_nand_cleanup;
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return 0;
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err_nand_cleanup:
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nand_cleanup(this);
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return err;
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}
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/*
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* Clean up routine
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*/
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static int ams_delta_cleanup(struct platform_device *pdev)
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{
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struct ams_delta_nand *priv = platform_get_drvdata(pdev);
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struct mtd_info *mtd = nand_to_mtd(&priv->nand_chip);
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/* Unregister device */
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nand_release(mtd_to_nand(mtd));
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return 0;
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}
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static struct platform_driver ams_delta_nand_driver = {
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.probe = ams_delta_init,
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.remove = ams_delta_cleanup,
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.driver = {
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.name = "ams-delta-nand",
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},
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};
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module_platform_driver(ams_delta_nand_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Jonathan McDowell <noodles@earth.li>");
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MODULE_DESCRIPTION("Glue layer for NAND flash on Amstrad E3 (Delta)");
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