273 lines
5.6 KiB
ArmAsm
273 lines
5.6 KiB
ArmAsm
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/*
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* arch/xtensa/kernel/coprocessor.S
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*
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* Xtensa processor configuration-specific table of coprocessor and
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* other custom register layout information.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 - 2007 Tensilica Inc.
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*/
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/asmmacro.h>
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#include <asm/processor.h>
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#include <asm/coprocessor.h>
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#include <asm/thread_info.h>
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#include <asm/asm-uaccess.h>
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#include <asm/unistd.h>
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#include <asm/ptrace.h>
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#include <asm/current.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/signal.h>
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#include <asm/tlbflush.h>
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#if XTENSA_HAVE_COPROCESSORS
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/*
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* Macros for lazy context switch.
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*/
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#define SAVE_CP_REGS(x) \
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.if XTENSA_HAVE_COPROCESSOR(x); \
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.align 4; \
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.Lsave_cp_regs_cp##x: \
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xchal_cp##x##_store a2 a4 a5 a6 a7; \
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jx a0; \
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.endif
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#define SAVE_CP_REGS_TAB(x) \
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.if XTENSA_HAVE_COPROCESSOR(x); \
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.long .Lsave_cp_regs_cp##x; \
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.else; \
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.long 0; \
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.endif; \
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.long THREAD_XTREGS_CP##x
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#define LOAD_CP_REGS(x) \
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.if XTENSA_HAVE_COPROCESSOR(x); \
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.align 4; \
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.Lload_cp_regs_cp##x: \
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xchal_cp##x##_load a2 a4 a5 a6 a7; \
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jx a0; \
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.endif
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#define LOAD_CP_REGS_TAB(x) \
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.if XTENSA_HAVE_COPROCESSOR(x); \
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.long .Lload_cp_regs_cp##x; \
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.else; \
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.long 0; \
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.endif; \
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.long THREAD_XTREGS_CP##x
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SAVE_CP_REGS(0)
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SAVE_CP_REGS(1)
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SAVE_CP_REGS(2)
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SAVE_CP_REGS(3)
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SAVE_CP_REGS(4)
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SAVE_CP_REGS(5)
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SAVE_CP_REGS(6)
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SAVE_CP_REGS(7)
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LOAD_CP_REGS(0)
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LOAD_CP_REGS(1)
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LOAD_CP_REGS(2)
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LOAD_CP_REGS(3)
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LOAD_CP_REGS(4)
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LOAD_CP_REGS(5)
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LOAD_CP_REGS(6)
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LOAD_CP_REGS(7)
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.section ".rodata", "a"
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.align 4
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.Lsave_cp_regs_jump_table:
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SAVE_CP_REGS_TAB(0)
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SAVE_CP_REGS_TAB(1)
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SAVE_CP_REGS_TAB(2)
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SAVE_CP_REGS_TAB(3)
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SAVE_CP_REGS_TAB(4)
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SAVE_CP_REGS_TAB(5)
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SAVE_CP_REGS_TAB(6)
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SAVE_CP_REGS_TAB(7)
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.Lload_cp_regs_jump_table:
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LOAD_CP_REGS_TAB(0)
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LOAD_CP_REGS_TAB(1)
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LOAD_CP_REGS_TAB(2)
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LOAD_CP_REGS_TAB(3)
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LOAD_CP_REGS_TAB(4)
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LOAD_CP_REGS_TAB(5)
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LOAD_CP_REGS_TAB(6)
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LOAD_CP_REGS_TAB(7)
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.previous
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/*
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* coprocessor_flush(struct thread_info*, index)
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* a2 a3
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*
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* Save coprocessor registers for coprocessor 'index'.
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* The register values are saved to or loaded from the coprocessor area
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* inside the task_info structure.
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*
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* Note that this function doesn't update the coprocessor_owner information!
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*
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*/
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ENTRY(coprocessor_flush)
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/* reserve 4 bytes on stack to save a0 */
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abi_entry(4)
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s32i a0, a1, 0
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movi a0, .Lsave_cp_regs_jump_table
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addx8 a3, a3, a0
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l32i a4, a3, 4
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l32i a3, a3, 0
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add a2, a2, a4
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beqz a3, 1f
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callx0 a3
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1: l32i a0, a1, 0
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abi_ret(4)
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ENDPROC(coprocessor_flush)
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/*
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* Entry condition:
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*
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* a0: trashed, original value saved on stack (PT_AREG0)
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* a1: a1
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* a2: new stack pointer, original in DEPC
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* a3: a3
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* depc: a2, original value saved on stack (PT_DEPC)
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* excsave_1: dispatch table
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*
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* PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
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* < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
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*/
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ENTRY(fast_coprocessor_double)
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wsr a0, excsave1
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call0 unrecoverable_exception
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ENDPROC(fast_coprocessor_double)
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ENTRY(fast_coprocessor)
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/* Save remaining registers a1-a3 and SAR */
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s32i a3, a2, PT_AREG3
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rsr a3, sar
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s32i a1, a2, PT_AREG1
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s32i a3, a2, PT_SAR
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mov a1, a2
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rsr a2, depc
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s32i a2, a1, PT_AREG2
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/*
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* The hal macros require up to 4 temporary registers. We use a3..a6.
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*/
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s32i a4, a1, PT_AREG4
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s32i a5, a1, PT_AREG5
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s32i a6, a1, PT_AREG6
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/* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */
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rsr a3, exccause
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addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
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/* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/
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ssl a3 # SAR: 32 - coprocessor_number
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movi a2, 1
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rsr a0, cpenable
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sll a2, a2
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or a0, a0, a2
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wsr a0, cpenable
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rsync
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/* Retrieve previous owner. (a3 still holds CP number) */
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movi a0, coprocessor_owner # list of owners
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addx4 a0, a3, a0 # entry for CP
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l32i a4, a0, 0
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beqz a4, 1f # skip 'save' if no previous owner
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/* Disable coprocessor for previous owner. (a2 = 1 << CP number) */
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l32i a5, a4, THREAD_CPENABLE
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xor a5, a5, a2 # (1 << cp-id) still in a2
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s32i a5, a4, THREAD_CPENABLE
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/*
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* Get context save area and 'call' save routine.
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* (a4 still holds previous owner (thread_info), a3 CP number)
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*/
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movi a5, .Lsave_cp_regs_jump_table
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movi a0, 2f # a0: 'return' address
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addx8 a3, a3, a5 # a3: coprocessor number
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l32i a2, a3, 4 # a2: xtregs offset
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l32i a3, a3, 0 # a3: jump address
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add a2, a2, a4
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jx a3
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/* Note that only a0 and a1 were preserved. */
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2: rsr a3, exccause
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addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
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movi a0, coprocessor_owner
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addx4 a0, a3, a0
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/* Set new 'owner' (a0 points to the CP owner, a3 contains the CP nr) */
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1: GET_THREAD_INFO (a4, a1)
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s32i a4, a0, 0
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/* Get context save area and 'call' load routine. */
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movi a5, .Lload_cp_regs_jump_table
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movi a0, 1f
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addx8 a3, a3, a5
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l32i a2, a3, 4 # a2: xtregs offset
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l32i a3, a3, 0 # a3: jump address
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add a2, a2, a4
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jx a3
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/* Restore all registers and return from exception handler. */
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1: l32i a6, a1, PT_AREG6
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l32i a5, a1, PT_AREG5
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l32i a4, a1, PT_AREG4
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l32i a0, a1, PT_SAR
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l32i a3, a1, PT_AREG3
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l32i a2, a1, PT_AREG2
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wsr a0, sar
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l32i a0, a1, PT_AREG0
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l32i a1, a1, PT_AREG1
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rfe
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ENDPROC(fast_coprocessor)
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.data
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ENTRY(coprocessor_owner)
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.fill XCHAL_CP_MAX, 4, 0
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END(coprocessor_owner)
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#endif /* XTENSA_HAVE_COPROCESSORS */
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