278 lines
9.0 KiB
C
278 lines
9.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* arch/sh/kernel/cpu/sh4a/clock-sh7343.c
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*
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* SH7343 clock framework support
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*
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* Copyright (C) 2009 Magnus Damm
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <asm/clock.h>
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/* SH7343 registers */
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#define FRQCR 0xa4150000
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#define VCLKCR 0xa4150004
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#define SCLKACR 0xa4150008
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#define SCLKBCR 0xa415000c
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#define PLLCR 0xa4150024
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#define MSTPCR0 0xa4150030
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#define MSTPCR1 0xa4150034
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#define MSTPCR2 0xa4150038
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#define DLLFRQ 0xa4150050
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/* Fixed 32 KHz root clock for RTC and Power Management purposes */
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static struct clk r_clk = {
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.rate = 32768,
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};
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/*
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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struct clk extal_clk = {
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.rate = 33333333,
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};
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/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
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static unsigned long dll_recalc(struct clk *clk)
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{
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unsigned long mult;
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if (__raw_readl(PLLCR) & 0x1000)
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mult = __raw_readl(DLLFRQ);
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else
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mult = 0;
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return clk->parent->rate * mult;
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}
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static struct sh_clk_ops dll_clk_ops = {
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.recalc = dll_recalc,
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};
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static struct clk dll_clk = {
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.ops = &dll_clk_ops,
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.parent = &r_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static unsigned long pll_recalc(struct clk *clk)
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{
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unsigned long mult = 1;
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if (__raw_readl(PLLCR) & 0x4000)
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mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
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return clk->parent->rate * mult;
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}
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static struct sh_clk_ops pll_clk_ops = {
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.recalc = pll_recalc,
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};
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static struct clk pll_clk = {
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.ops = &pll_clk_ops,
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.flags = CLK_ENABLE_ON_INIT,
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};
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struct clk *main_clks[] = {
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&r_clk,
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&extal_clk,
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&dll_clk,
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&pll_clk,
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};
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static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
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static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = divisors,
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.nr_divisors = ARRAY_SIZE(divisors),
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.multipliers = multipliers,
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.nr_multipliers = ARRAY_SIZE(multipliers),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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};
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enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
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DIV4_SIUA, DIV4_SIUB, DIV4_NR };
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#define DIV4(_reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
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[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
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[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
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};
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enum { DIV6_V, DIV6_NR };
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struct clk div6_clks[DIV6_NR] = {
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[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
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};
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#define MSTP(_parent, _reg, _bit, _flags) \
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SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
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enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
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MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
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MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
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MSTP007, MSTP006, MSTP005, MSTP004, MSTP003, MSTP002, MSTP001,
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MSTP109, MSTP108, MSTP100,
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MSTP225, MSTP224, MSTP218, MSTP217, MSTP216,
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MSTP214, MSTP213, MSTP212, MSTP211, MSTP208,
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MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
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MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
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[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
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[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
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[MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
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[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
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[MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
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[MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
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[MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
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[MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
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[MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
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[MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
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[MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
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[MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
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[MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
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[MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
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[MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
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[MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
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[MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
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[MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
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[MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
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[MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
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[MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
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[MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
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[MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
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[MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
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[MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0),
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[MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
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[MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
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[MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
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[MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0),
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[MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
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[MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0),
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[MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0),
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[MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
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[MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
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[MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
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[MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
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[MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
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[MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
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[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
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[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
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[MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
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};
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("rclk", &r_clk),
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CLKDEV_CON_ID("extal", &extal_clk),
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CLKDEV_CON_ID("dll_clk", &dll_clk),
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CLKDEV_CON_ID("pll_clk", &pll_clk),
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/* DIV4 clocks */
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CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
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CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
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CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
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CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
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CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
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CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
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/* DIV6 clocks */
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CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
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/* MSTP32 clocks */
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CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
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CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
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CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
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CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]),
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CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
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CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
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CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
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CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
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CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
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CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
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CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
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CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
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CLKDEV_ICK_ID("fck", "sh-cmt-32.0", &mstp_clks[MSTP014]),
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CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
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CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
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CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
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CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP007]),
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CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP006]),
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CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP005]),
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CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP004]),
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CLKDEV_CON_ID("sio0", &mstp_clks[MSTP003]),
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CLKDEV_CON_ID("siof0", &mstp_clks[MSTP002]),
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CLKDEV_CON_ID("siof1", &mstp_clks[MSTP001]),
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CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP109]),
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CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP108]),
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CLKDEV_CON_ID("tpu0", &mstp_clks[MSTP225]),
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CLKDEV_CON_ID("irda0", &mstp_clks[MSTP224]),
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CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
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CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
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CLKDEV_CON_ID("sim0", &mstp_clks[MSTP216]),
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CLKDEV_CON_ID("keysc0", &mstp_clks[MSTP214]),
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CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP213]),
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CLKDEV_CON_ID("s3d40", &mstp_clks[MSTP212]),
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CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
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CLKDEV_CON_ID("siu0", &mstp_clks[MSTP208]),
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CLKDEV_CON_ID("jpu0", &mstp_clks[MSTP206]),
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CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
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CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
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CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
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CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
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CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
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CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
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};
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int __init arch_clk_init(void)
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{
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int k, ret = 0;
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/* autodetect extal or dll configuration */
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if (__raw_readl(PLLCR) & 0x1000)
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pll_clk.parent = &dll_clk;
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else
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pll_clk.parent = &extal_clk;
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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if (!ret)
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ret = sh_clk_div6_register(div6_clks, DIV6_NR);
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if (!ret)
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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return ret;
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}
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