562 lines
13 KiB
C
562 lines
13 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_ATOMIC_H_
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#define _ASM_POWERPC_ATOMIC_H_
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/*
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* PowerPC atomic operations
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*/
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#ifdef __KERNEL__
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#include <linux/types.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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#include <asm/asm-405.h>
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#define ATOMIC_INIT(i) { (i) }
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/*
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* Since *_return_relaxed and {cmp}xchg_relaxed are implemented with
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* a "bne-" instruction at the end, so an isync is enough as a acquire barrier
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* on the platform without lwsync.
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*/
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#define __atomic_acquire_fence() \
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__asm__ __volatile__(PPC_ACQUIRE_BARRIER "" : : : "memory")
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#define __atomic_release_fence() \
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__asm__ __volatile__(PPC_RELEASE_BARRIER "" : : : "memory")
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static __inline__ int atomic_read(const atomic_t *v)
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{
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int t;
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__asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter));
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return t;
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}
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static __inline__ void atomic_set(atomic_t *v, int i)
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{
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__asm__ __volatile__("stw%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i));
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}
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#define ATOMIC_OP(op, asm_op) \
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static __inline__ void atomic_##op(int a, atomic_t *v) \
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{ \
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int t; \
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\
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__asm__ __volatile__( \
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"1: lwarx %0,0,%3 # atomic_" #op "\n" \
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#asm_op " %0,%2,%0\n" \
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PPC405_ERR77(0,%3) \
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" stwcx. %0,0,%3 \n" \
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" bne- 1b\n" \
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: "=&r" (t), "+m" (v->counter) \
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: "r" (a), "r" (&v->counter) \
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: "cc"); \
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} \
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#define ATOMIC_OP_RETURN_RELAXED(op, asm_op) \
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static inline int atomic_##op##_return_relaxed(int a, atomic_t *v) \
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{ \
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int t; \
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\
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__asm__ __volatile__( \
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"1: lwarx %0,0,%3 # atomic_" #op "_return_relaxed\n" \
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#asm_op " %0,%2,%0\n" \
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PPC405_ERR77(0, %3) \
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" stwcx. %0,0,%3\n" \
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" bne- 1b\n" \
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: "=&r" (t), "+m" (v->counter) \
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: "r" (a), "r" (&v->counter) \
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: "cc"); \
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\
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return t; \
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}
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#define ATOMIC_FETCH_OP_RELAXED(op, asm_op) \
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static inline int atomic_fetch_##op##_relaxed(int a, atomic_t *v) \
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{ \
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int res, t; \
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\
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__asm__ __volatile__( \
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"1: lwarx %0,0,%4 # atomic_fetch_" #op "_relaxed\n" \
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#asm_op " %1,%3,%0\n" \
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PPC405_ERR77(0, %4) \
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" stwcx. %1,0,%4\n" \
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" bne- 1b\n" \
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: "=&r" (res), "=&r" (t), "+m" (v->counter) \
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: "r" (a), "r" (&v->counter) \
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: "cc"); \
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\
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return res; \
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}
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#define ATOMIC_OPS(op, asm_op) \
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ATOMIC_OP(op, asm_op) \
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ATOMIC_OP_RETURN_RELAXED(op, asm_op) \
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ATOMIC_FETCH_OP_RELAXED(op, asm_op)
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ATOMIC_OPS(add, add)
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ATOMIC_OPS(sub, subf)
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#define atomic_add_return_relaxed atomic_add_return_relaxed
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#define atomic_sub_return_relaxed atomic_sub_return_relaxed
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#define atomic_fetch_add_relaxed atomic_fetch_add_relaxed
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#define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, asm_op) \
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ATOMIC_OP(op, asm_op) \
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ATOMIC_FETCH_OP_RELAXED(op, asm_op)
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ATOMIC_OPS(and, and)
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ATOMIC_OPS(or, or)
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ATOMIC_OPS(xor, xor)
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#define atomic_fetch_and_relaxed atomic_fetch_and_relaxed
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#define atomic_fetch_or_relaxed atomic_fetch_or_relaxed
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#define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP_RELAXED
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#undef ATOMIC_OP_RETURN_RELAXED
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#undef ATOMIC_OP
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static __inline__ void atomic_inc(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_inc\n\
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addic %0,%0,1\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (&v->counter)
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: "cc", "xer");
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}
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#define atomic_inc atomic_inc
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static __inline__ int atomic_inc_return_relaxed(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_inc_return_relaxed\n"
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" addic %0,%0,1\n"
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PPC405_ERR77(0, %2)
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" stwcx. %0,0,%2\n"
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" bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (&v->counter)
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: "cc", "xer");
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return t;
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}
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static __inline__ void atomic_dec(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_dec\n\
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addic %0,%0,-1\n"
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PPC405_ERR77(0,%2)\
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" stwcx. %0,0,%2\n\
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bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (&v->counter)
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: "cc", "xer");
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}
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#define atomic_dec atomic_dec
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static __inline__ int atomic_dec_return_relaxed(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_dec_return_relaxed\n"
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" addic %0,%0,-1\n"
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PPC405_ERR77(0, %2)
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" stwcx. %0,0,%2\n"
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" bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (&v->counter)
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: "cc", "xer");
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return t;
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}
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#define atomic_inc_return_relaxed atomic_inc_return_relaxed
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#define atomic_dec_return_relaxed atomic_dec_return_relaxed
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#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
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#define atomic_cmpxchg_relaxed(v, o, n) \
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cmpxchg_relaxed(&((v)->counter), (o), (n))
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#define atomic_cmpxchg_acquire(v, o, n) \
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cmpxchg_acquire(&((v)->counter), (o), (n))
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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#define atomic_xchg_relaxed(v, new) xchg_relaxed(&((v)->counter), (new))
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/**
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* atomic_fetch_add_unless - add unless the number is a given value
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* @v: pointer of type atomic_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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* Returns the old value of @v.
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*/
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static __inline__ int atomic_fetch_add_unless(atomic_t *v, int a, int u)
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{
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int t;
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__asm__ __volatile__ (
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PPC_ATOMIC_ENTRY_BARRIER
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"1: lwarx %0,0,%1 # atomic_fetch_add_unless\n\
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cmpw 0,%0,%3 \n\
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beq 2f \n\
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add %0,%2,%0 \n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%1 \n\
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bne- 1b \n"
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PPC_ATOMIC_EXIT_BARRIER
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" subf %0,%2,%0 \n\
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2:"
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: "=&r" (t)
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: "r" (&v->counter), "r" (a), "r" (u)
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: "cc", "memory");
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return t;
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}
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#define atomic_fetch_add_unless atomic_fetch_add_unless
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/**
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* atomic_inc_not_zero - increment unless the number is zero
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1, so long as @v is non-zero.
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* Returns non-zero if @v was non-zero, and zero otherwise.
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*/
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static __inline__ int atomic_inc_not_zero(atomic_t *v)
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{
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int t1, t2;
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__asm__ __volatile__ (
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PPC_ATOMIC_ENTRY_BARRIER
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"1: lwarx %0,0,%2 # atomic_inc_not_zero\n\
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cmpwi 0,%0,0\n\
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beq- 2f\n\
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addic %1,%0,1\n"
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PPC405_ERR77(0,%2)
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" stwcx. %1,0,%2\n\
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bne- 1b\n"
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PPC_ATOMIC_EXIT_BARRIER
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"\n\
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2:"
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: "=&r" (t1), "=&r" (t2)
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: "r" (&v->counter)
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: "cc", "xer", "memory");
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return t1;
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}
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#define atomic_inc_not_zero(v) atomic_inc_not_zero((v))
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/*
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* Atomically test *v and decrement if it is greater than 0.
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* The function returns the old value of *v minus 1, even if
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* the atomic variable, v, was not decremented.
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*/
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static __inline__ int atomic_dec_if_positive(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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PPC_ATOMIC_ENTRY_BARRIER
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"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
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cmpwi %0,1\n\
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addi %0,%0,-1\n\
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blt- 2f\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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PPC_ATOMIC_EXIT_BARRIER
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"\n\
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2:" : "=&b" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define atomic_dec_if_positive atomic_dec_if_positive
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#ifdef __powerpc64__
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#define ATOMIC64_INIT(i) { (i) }
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static __inline__ s64 atomic64_read(const atomic64_t *v)
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{
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s64 t;
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__asm__ __volatile__("ld%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter));
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return t;
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}
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static __inline__ void atomic64_set(atomic64_t *v, s64 i)
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{
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__asm__ __volatile__("std%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i));
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}
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#define ATOMIC64_OP(op, asm_op) \
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static __inline__ void atomic64_##op(s64 a, atomic64_t *v) \
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{ \
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s64 t; \
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\
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__asm__ __volatile__( \
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"1: ldarx %0,0,%3 # atomic64_" #op "\n" \
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#asm_op " %0,%2,%0\n" \
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" stdcx. %0,0,%3 \n" \
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" bne- 1b\n" \
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: "=&r" (t), "+m" (v->counter) \
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: "r" (a), "r" (&v->counter) \
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: "cc"); \
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}
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#define ATOMIC64_OP_RETURN_RELAXED(op, asm_op) \
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static inline s64 \
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atomic64_##op##_return_relaxed(s64 a, atomic64_t *v) \
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{ \
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s64 t; \
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\
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__asm__ __volatile__( \
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"1: ldarx %0,0,%3 # atomic64_" #op "_return_relaxed\n" \
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#asm_op " %0,%2,%0\n" \
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" stdcx. %0,0,%3\n" \
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" bne- 1b\n" \
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: "=&r" (t), "+m" (v->counter) \
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: "r" (a), "r" (&v->counter) \
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: "cc"); \
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\
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return t; \
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}
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#define ATOMIC64_FETCH_OP_RELAXED(op, asm_op) \
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static inline s64 \
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atomic64_fetch_##op##_relaxed(s64 a, atomic64_t *v) \
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{ \
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s64 res, t; \
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\
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__asm__ __volatile__( \
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"1: ldarx %0,0,%4 # atomic64_fetch_" #op "_relaxed\n" \
|
||
|
|
#asm_op " %1,%3,%0\n" \
|
||
|
|
" stdcx. %1,0,%4\n" \
|
||
|
|
" bne- 1b\n" \
|
||
|
|
: "=&r" (res), "=&r" (t), "+m" (v->counter) \
|
||
|
|
: "r" (a), "r" (&v->counter) \
|
||
|
|
: "cc"); \
|
||
|
|
\
|
||
|
|
return res; \
|
||
|
|
}
|
||
|
|
|
||
|
|
#define ATOMIC64_OPS(op, asm_op) \
|
||
|
|
ATOMIC64_OP(op, asm_op) \
|
||
|
|
ATOMIC64_OP_RETURN_RELAXED(op, asm_op) \
|
||
|
|
ATOMIC64_FETCH_OP_RELAXED(op, asm_op)
|
||
|
|
|
||
|
|
ATOMIC64_OPS(add, add)
|
||
|
|
ATOMIC64_OPS(sub, subf)
|
||
|
|
|
||
|
|
#define atomic64_add_return_relaxed atomic64_add_return_relaxed
|
||
|
|
#define atomic64_sub_return_relaxed atomic64_sub_return_relaxed
|
||
|
|
|
||
|
|
#define atomic64_fetch_add_relaxed atomic64_fetch_add_relaxed
|
||
|
|
#define atomic64_fetch_sub_relaxed atomic64_fetch_sub_relaxed
|
||
|
|
|
||
|
|
#undef ATOMIC64_OPS
|
||
|
|
#define ATOMIC64_OPS(op, asm_op) \
|
||
|
|
ATOMIC64_OP(op, asm_op) \
|
||
|
|
ATOMIC64_FETCH_OP_RELAXED(op, asm_op)
|
||
|
|
|
||
|
|
ATOMIC64_OPS(and, and)
|
||
|
|
ATOMIC64_OPS(or, or)
|
||
|
|
ATOMIC64_OPS(xor, xor)
|
||
|
|
|
||
|
|
#define atomic64_fetch_and_relaxed atomic64_fetch_and_relaxed
|
||
|
|
#define atomic64_fetch_or_relaxed atomic64_fetch_or_relaxed
|
||
|
|
#define atomic64_fetch_xor_relaxed atomic64_fetch_xor_relaxed
|
||
|
|
|
||
|
|
#undef ATOPIC64_OPS
|
||
|
|
#undef ATOMIC64_FETCH_OP_RELAXED
|
||
|
|
#undef ATOMIC64_OP_RETURN_RELAXED
|
||
|
|
#undef ATOMIC64_OP
|
||
|
|
|
||
|
|
static __inline__ void atomic64_inc(atomic64_t *v)
|
||
|
|
{
|
||
|
|
s64 t;
|
||
|
|
|
||
|
|
__asm__ __volatile__(
|
||
|
|
"1: ldarx %0,0,%2 # atomic64_inc\n\
|
||
|
|
addic %0,%0,1\n\
|
||
|
|
stdcx. %0,0,%2 \n\
|
||
|
|
bne- 1b"
|
||
|
|
: "=&r" (t), "+m" (v->counter)
|
||
|
|
: "r" (&v->counter)
|
||
|
|
: "cc", "xer");
|
||
|
|
}
|
||
|
|
#define atomic64_inc atomic64_inc
|
||
|
|
|
||
|
|
static __inline__ s64 atomic64_inc_return_relaxed(atomic64_t *v)
|
||
|
|
{
|
||
|
|
s64 t;
|
||
|
|
|
||
|
|
__asm__ __volatile__(
|
||
|
|
"1: ldarx %0,0,%2 # atomic64_inc_return_relaxed\n"
|
||
|
|
" addic %0,%0,1\n"
|
||
|
|
" stdcx. %0,0,%2\n"
|
||
|
|
" bne- 1b"
|
||
|
|
: "=&r" (t), "+m" (v->counter)
|
||
|
|
: "r" (&v->counter)
|
||
|
|
: "cc", "xer");
|
||
|
|
|
||
|
|
return t;
|
||
|
|
}
|
||
|
|
|
||
|
|
static __inline__ void atomic64_dec(atomic64_t *v)
|
||
|
|
{
|
||
|
|
s64 t;
|
||
|
|
|
||
|
|
__asm__ __volatile__(
|
||
|
|
"1: ldarx %0,0,%2 # atomic64_dec\n\
|
||
|
|
addic %0,%0,-1\n\
|
||
|
|
stdcx. %0,0,%2\n\
|
||
|
|
bne- 1b"
|
||
|
|
: "=&r" (t), "+m" (v->counter)
|
||
|
|
: "r" (&v->counter)
|
||
|
|
: "cc", "xer");
|
||
|
|
}
|
||
|
|
#define atomic64_dec atomic64_dec
|
||
|
|
|
||
|
|
static __inline__ s64 atomic64_dec_return_relaxed(atomic64_t *v)
|
||
|
|
{
|
||
|
|
s64 t;
|
||
|
|
|
||
|
|
__asm__ __volatile__(
|
||
|
|
"1: ldarx %0,0,%2 # atomic64_dec_return_relaxed\n"
|
||
|
|
" addic %0,%0,-1\n"
|
||
|
|
" stdcx. %0,0,%2\n"
|
||
|
|
" bne- 1b"
|
||
|
|
: "=&r" (t), "+m" (v->counter)
|
||
|
|
: "r" (&v->counter)
|
||
|
|
: "cc", "xer");
|
||
|
|
|
||
|
|
return t;
|
||
|
|
}
|
||
|
|
|
||
|
|
#define atomic64_inc_return_relaxed atomic64_inc_return_relaxed
|
||
|
|
#define atomic64_dec_return_relaxed atomic64_dec_return_relaxed
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Atomically test *v and decrement if it is greater than 0.
|
||
|
|
* The function returns the old value of *v minus 1.
|
||
|
|
*/
|
||
|
|
static __inline__ s64 atomic64_dec_if_positive(atomic64_t *v)
|
||
|
|
{
|
||
|
|
s64 t;
|
||
|
|
|
||
|
|
__asm__ __volatile__(
|
||
|
|
PPC_ATOMIC_ENTRY_BARRIER
|
||
|
|
"1: ldarx %0,0,%1 # atomic64_dec_if_positive\n\
|
||
|
|
addic. %0,%0,-1\n\
|
||
|
|
blt- 2f\n\
|
||
|
|
stdcx. %0,0,%1\n\
|
||
|
|
bne- 1b"
|
||
|
|
PPC_ATOMIC_EXIT_BARRIER
|
||
|
|
"\n\
|
||
|
|
2:" : "=&r" (t)
|
||
|
|
: "r" (&v->counter)
|
||
|
|
: "cc", "xer", "memory");
|
||
|
|
|
||
|
|
return t;
|
||
|
|
}
|
||
|
|
#define atomic64_dec_if_positive atomic64_dec_if_positive
|
||
|
|
|
||
|
|
#define atomic64_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
|
||
|
|
#define atomic64_cmpxchg_relaxed(v, o, n) \
|
||
|
|
cmpxchg_relaxed(&((v)->counter), (o), (n))
|
||
|
|
#define atomic64_cmpxchg_acquire(v, o, n) \
|
||
|
|
cmpxchg_acquire(&((v)->counter), (o), (n))
|
||
|
|
|
||
|
|
#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
|
||
|
|
#define atomic64_xchg_relaxed(v, new) xchg_relaxed(&((v)->counter), (new))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* atomic64_fetch_add_unless - add unless the number is a given value
|
||
|
|
* @v: pointer of type atomic64_t
|
||
|
|
* @a: the amount to add to v...
|
||
|
|
* @u: ...unless v is equal to u.
|
||
|
|
*
|
||
|
|
* Atomically adds @a to @v, so long as it was not @u.
|
||
|
|
* Returns the old value of @v.
|
||
|
|
*/
|
||
|
|
static __inline__ s64 atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
|
||
|
|
{
|
||
|
|
s64 t;
|
||
|
|
|
||
|
|
__asm__ __volatile__ (
|
||
|
|
PPC_ATOMIC_ENTRY_BARRIER
|
||
|
|
"1: ldarx %0,0,%1 # atomic64_fetch_add_unless\n\
|
||
|
|
cmpd 0,%0,%3 \n\
|
||
|
|
beq 2f \n\
|
||
|
|
add %0,%2,%0 \n"
|
||
|
|
" stdcx. %0,0,%1 \n\
|
||
|
|
bne- 1b \n"
|
||
|
|
PPC_ATOMIC_EXIT_BARRIER
|
||
|
|
" subf %0,%2,%0 \n\
|
||
|
|
2:"
|
||
|
|
: "=&r" (t)
|
||
|
|
: "r" (&v->counter), "r" (a), "r" (u)
|
||
|
|
: "cc", "memory");
|
||
|
|
|
||
|
|
return t;
|
||
|
|
}
|
||
|
|
#define atomic64_fetch_add_unless atomic64_fetch_add_unless
|
||
|
|
|
||
|
|
/**
|
||
|
|
* atomic_inc64_not_zero - increment unless the number is zero
|
||
|
|
* @v: pointer of type atomic64_t
|
||
|
|
*
|
||
|
|
* Atomically increments @v by 1, so long as @v is non-zero.
|
||
|
|
* Returns non-zero if @v was non-zero, and zero otherwise.
|
||
|
|
*/
|
||
|
|
static __inline__ int atomic64_inc_not_zero(atomic64_t *v)
|
||
|
|
{
|
||
|
|
s64 t1, t2;
|
||
|
|
|
||
|
|
__asm__ __volatile__ (
|
||
|
|
PPC_ATOMIC_ENTRY_BARRIER
|
||
|
|
"1: ldarx %0,0,%2 # atomic64_inc_not_zero\n\
|
||
|
|
cmpdi 0,%0,0\n\
|
||
|
|
beq- 2f\n\
|
||
|
|
addic %1,%0,1\n\
|
||
|
|
stdcx. %1,0,%2\n\
|
||
|
|
bne- 1b\n"
|
||
|
|
PPC_ATOMIC_EXIT_BARRIER
|
||
|
|
"\n\
|
||
|
|
2:"
|
||
|
|
: "=&r" (t1), "=&r" (t2)
|
||
|
|
: "r" (&v->counter)
|
||
|
|
: "cc", "xer", "memory");
|
||
|
|
|
||
|
|
return t1 != 0;
|
||
|
|
}
|
||
|
|
#define atomic64_inc_not_zero(v) atomic64_inc_not_zero((v))
|
||
|
|
|
||
|
|
#endif /* __powerpc64__ */
|
||
|
|
|
||
|
|
#endif /* __KERNEL__ */
|
||
|
|
#endif /* _ASM_POWERPC_ATOMIC_H_ */
|