534 lines
12 KiB
C
534 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2005-2017 Andes Technology Corporation
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/nds32.h>
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#include <asm/pgtable.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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#include <asm/l2_cache.h>
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#include <nds32_intrinsic.h>
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#include <asm/cache_info.h>
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extern struct cache_info L1_cache_info[2];
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int va_kernel_present(unsigned long addr)
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{
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pmd_t *pmd;
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pte_t *ptep, pte;
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pmd = pmd_offset(pgd_offset_k(addr), addr);
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if (!pmd_none(*pmd)) {
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ptep = pte_offset_map(pmd, addr);
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pte = *ptep;
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if (pte_present(pte))
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return pte;
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}
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return 0;
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}
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pte_t va_present(struct mm_struct * mm, unsigned long addr)
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{
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *ptep, pte;
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pgd = pgd_offset(mm, addr);
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if (!pgd_none(*pgd)) {
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pud = pud_offset(pgd, addr);
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if (!pud_none(*pud)) {
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pmd = pmd_offset(pud, addr);
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if (!pmd_none(*pmd)) {
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ptep = pte_offset_map(pmd, addr);
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pte = *ptep;
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if (pte_present(pte))
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return pte;
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}
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}
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}
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return 0;
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}
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int va_readable(struct pt_regs *regs, unsigned long addr)
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{
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struct mm_struct *mm = current->mm;
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pte_t pte;
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int ret = 0;
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if (user_mode(regs)) {
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/* user mode */
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pte = va_present(mm, addr);
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if (!pte && pte_read(pte))
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ret = 1;
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} else {
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/* superuser mode is always readable, so we can only
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* check it is present or not*/
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return (! !va_kernel_present(addr));
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}
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return ret;
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}
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int va_writable(struct pt_regs *regs, unsigned long addr)
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{
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struct mm_struct *mm = current->mm;
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pte_t pte;
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int ret = 0;
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if (user_mode(regs)) {
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/* user mode */
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pte = va_present(mm, addr);
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if (!pte && pte_write(pte))
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ret = 1;
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} else {
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/* superuser mode */
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pte = va_kernel_present(addr);
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if (!pte && pte_kernel_write(pte))
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ret = 1;
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}
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return ret;
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}
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/*
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* All
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*/
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void cpu_icache_inval_all(void)
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{
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unsigned long end, line_size;
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line_size = L1_cache_info[ICACHE].line_size;
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end =
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line_size * L1_cache_info[ICACHE].ways * L1_cache_info[ICACHE].sets;
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do {
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end));
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} while (end > 0);
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__nds32__isb();
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}
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void cpu_dcache_inval_all(void)
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{
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__nds32__cctl_l1d_invalall();
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}
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#ifdef CONFIG_CACHE_L2
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void dcache_wb_all_level(void)
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{
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unsigned long flags, cmd;
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local_irq_save(flags);
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__nds32__cctl_l1d_wball_alvl();
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/* Section 1: Ensure the section 2 & 3 program code execution after */
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__nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
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/* Section 2: Confirm the writeback all level is done in CPU and L2C */
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cmd = CCTL_CMD_L2_SYNC;
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L2_CMD_RDY();
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L2C_W_REG(L2_CCTL_CMD_OFF, cmd);
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L2_CMD_RDY();
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/* Section 3: Writeback whole L2 cache */
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cmd = CCTL_ALL_CMD | CCTL_CMD_L2_IX_WB;
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L2_CMD_RDY();
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L2C_W_REG(L2_CCTL_CMD_OFF, cmd);
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L2_CMD_RDY();
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__nds32__msync_all();
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL(dcache_wb_all_level);
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#endif
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void cpu_dcache_wb_all(void)
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{
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__nds32__cctl_l1d_wball_one_lvl();
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__nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
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}
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void cpu_dcache_wbinval_all(void)
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{
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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unsigned long flags;
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local_irq_save(flags);
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#endif
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cpu_dcache_wb_all();
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cpu_dcache_inval_all();
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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local_irq_restore(flags);
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#endif
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}
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/*
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* Page
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*/
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void cpu_icache_inval_page(unsigned long start)
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{
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unsigned long line_size, end;
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line_size = L1_cache_info[ICACHE].line_size;
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end = start + PAGE_SIZE;
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do {
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end));
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} while (end != start);
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__nds32__isb();
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}
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void cpu_dcache_inval_page(unsigned long start)
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{
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unsigned long line_size, end;
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line_size = L1_cache_info[DCACHE].line_size;
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end = start + PAGE_SIZE;
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do {
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
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} while (end != start);
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}
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void cpu_dcache_wb_page(unsigned long start)
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{
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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unsigned long line_size, end;
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line_size = L1_cache_info[DCACHE].line_size;
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end = start + PAGE_SIZE;
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do {
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
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end -= line_size;
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__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
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} while (end != start);
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__nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
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#endif
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}
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void cpu_dcache_wbinval_page(unsigned long start)
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{
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unsigned long line_size, end;
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line_size = L1_cache_info[DCACHE].line_size;
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end = start + PAGE_SIZE;
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do {
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end -= line_size;
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
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#endif
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__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
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end -= line_size;
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
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#endif
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__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
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end -= line_size;
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
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#endif
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__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
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end -= line_size;
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
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#endif
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__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
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} while (end != start);
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__nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
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}
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void cpu_cache_wbinval_page(unsigned long page, int flushi)
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{
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cpu_dcache_wbinval_page(page);
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if (flushi)
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cpu_icache_inval_page(page);
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}
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/*
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* Range
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*/
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void cpu_icache_inval_range(unsigned long start, unsigned long end)
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{
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unsigned long line_size;
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line_size = L1_cache_info[ICACHE].line_size;
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while (end > start) {
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__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (start));
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start += line_size;
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}
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__nds32__isb();
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}
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void cpu_dcache_inval_range(unsigned long start, unsigned long end)
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{
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unsigned long line_size;
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line_size = L1_cache_info[DCACHE].line_size;
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while (end > start) {
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__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (start));
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start += line_size;
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}
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}
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void cpu_dcache_wb_range(unsigned long start, unsigned long end)
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{
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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unsigned long line_size;
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line_size = L1_cache_info[DCACHE].line_size;
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while (end > start) {
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__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (start));
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start += line_size;
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}
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__nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
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#endif
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}
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void cpu_dcache_wbinval_range(unsigned long start, unsigned long end)
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{
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unsigned long line_size;
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line_size = L1_cache_info[DCACHE].line_size;
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while (end > start) {
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (start));
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#endif
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__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (start));
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start += line_size;
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}
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__nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
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}
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void cpu_cache_wbinval_range(unsigned long start, unsigned long end, int flushi)
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{
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unsigned long line_size, align_start, align_end;
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line_size = L1_cache_info[DCACHE].line_size;
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align_start = start & ~(line_size - 1);
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align_end = (end + line_size - 1) & ~(line_size - 1);
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cpu_dcache_wbinval_range(align_start, align_end);
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if (flushi) {
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line_size = L1_cache_info[ICACHE].line_size;
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align_start = start & ~(line_size - 1);
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align_end = (end + line_size - 1) & ~(line_size - 1);
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cpu_icache_inval_range(align_start, align_end);
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}
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}
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void cpu_cache_wbinval_range_check(struct vm_area_struct *vma,
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unsigned long start, unsigned long end,
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bool flushi, bool wbd)
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{
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unsigned long line_size, t_start, t_end;
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if (!flushi && !wbd)
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return;
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line_size = L1_cache_info[DCACHE].line_size;
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start = start & ~(line_size - 1);
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end = (end + line_size - 1) & ~(line_size - 1);
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if ((end - start) > (8 * PAGE_SIZE)) {
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if (wbd)
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cpu_dcache_wbinval_all();
|
||
|
|
if (flushi)
|
||
|
|
cpu_icache_inval_all();
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
t_start = (start + PAGE_SIZE) & PAGE_MASK;
|
||
|
|
t_end = ((end - 1) & PAGE_MASK);
|
||
|
|
|
||
|
|
if ((start & PAGE_MASK) == t_end) {
|
||
|
|
if (va_present(vma->vm_mm, start)) {
|
||
|
|
if (wbd)
|
||
|
|
cpu_dcache_wbinval_range(start, end);
|
||
|
|
if (flushi)
|
||
|
|
cpu_icache_inval_range(start, end);
|
||
|
|
}
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (va_present(vma->vm_mm, start)) {
|
||
|
|
if (wbd)
|
||
|
|
cpu_dcache_wbinval_range(start, t_start);
|
||
|
|
if (flushi)
|
||
|
|
cpu_icache_inval_range(start, t_start);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (va_present(vma->vm_mm, end - 1)) {
|
||
|
|
if (wbd)
|
||
|
|
cpu_dcache_wbinval_range(t_end, end);
|
||
|
|
if (flushi)
|
||
|
|
cpu_icache_inval_range(t_end, end);
|
||
|
|
}
|
||
|
|
|
||
|
|
while (t_start < t_end) {
|
||
|
|
if (va_present(vma->vm_mm, t_start)) {
|
||
|
|
if (wbd)
|
||
|
|
cpu_dcache_wbinval_page(t_start);
|
||
|
|
if (flushi)
|
||
|
|
cpu_icache_inval_page(t_start);
|
||
|
|
}
|
||
|
|
t_start += PAGE_SIZE;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_CACHE_L2
|
||
|
|
static inline void cpu_l2cache_op(unsigned long start, unsigned long end, unsigned long op)
|
||
|
|
{
|
||
|
|
if (atl2c_base) {
|
||
|
|
unsigned long p_start = __pa(start);
|
||
|
|
unsigned long p_end = __pa(end);
|
||
|
|
unsigned long cmd;
|
||
|
|
unsigned long line_size;
|
||
|
|
/* TODO Can Use PAGE Mode to optimize if range large than PAGE_SIZE */
|
||
|
|
line_size = L2_CACHE_LINE_SIZE();
|
||
|
|
p_start = p_start & (~(line_size - 1));
|
||
|
|
p_end = (p_end + line_size - 1) & (~(line_size - 1));
|
||
|
|
cmd =
|
||
|
|
(p_start & ~(line_size - 1)) | op |
|
||
|
|
CCTL_SINGLE_CMD;
|
||
|
|
do {
|
||
|
|
L2_CMD_RDY();
|
||
|
|
L2C_W_REG(L2_CCTL_CMD_OFF, cmd);
|
||
|
|
cmd += line_size;
|
||
|
|
p_start += line_size;
|
||
|
|
} while (p_end > p_start);
|
||
|
|
cmd = CCTL_CMD_L2_SYNC;
|
||
|
|
L2_CMD_RDY();
|
||
|
|
L2C_W_REG(L2_CCTL_CMD_OFF, cmd);
|
||
|
|
L2_CMD_RDY();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#else
|
||
|
|
#define cpu_l2cache_op(start,end,op) do { } while (0)
|
||
|
|
#endif
|
||
|
|
/*
|
||
|
|
* DMA
|
||
|
|
*/
|
||
|
|
void cpu_dma_wb_range(unsigned long start, unsigned long end)
|
||
|
|
{
|
||
|
|
unsigned long line_size;
|
||
|
|
unsigned long flags;
|
||
|
|
line_size = L1_cache_info[DCACHE].line_size;
|
||
|
|
start = start & (~(line_size - 1));
|
||
|
|
end = (end + line_size - 1) & (~(line_size - 1));
|
||
|
|
if (unlikely(start == end))
|
||
|
|
return;
|
||
|
|
|
||
|
|
local_irq_save(flags);
|
||
|
|
cpu_dcache_wb_range(start, end);
|
||
|
|
cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_WB);
|
||
|
|
__nds32__msync_all();
|
||
|
|
local_irq_restore(flags);
|
||
|
|
}
|
||
|
|
|
||
|
|
void cpu_dma_inval_range(unsigned long start, unsigned long end)
|
||
|
|
{
|
||
|
|
unsigned long line_size;
|
||
|
|
unsigned long old_start = start;
|
||
|
|
unsigned long old_end = end;
|
||
|
|
unsigned long flags;
|
||
|
|
line_size = L1_cache_info[DCACHE].line_size;
|
||
|
|
start = start & (~(line_size - 1));
|
||
|
|
end = (end + line_size - 1) & (~(line_size - 1));
|
||
|
|
if (unlikely(start == end))
|
||
|
|
return;
|
||
|
|
local_irq_save(flags);
|
||
|
|
if (start != old_start) {
|
||
|
|
cpu_dcache_wbinval_range(start, start + line_size);
|
||
|
|
cpu_l2cache_op(start, start + line_size, CCTL_CMD_L2_PA_WBINVAL);
|
||
|
|
}
|
||
|
|
if (end != old_end) {
|
||
|
|
cpu_dcache_wbinval_range(end - line_size, end);
|
||
|
|
cpu_l2cache_op(end - line_size, end, CCTL_CMD_L2_PA_WBINVAL);
|
||
|
|
}
|
||
|
|
cpu_dcache_inval_range(start, end);
|
||
|
|
cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_INVAL);
|
||
|
|
__nds32__msync_all();
|
||
|
|
local_irq_restore(flags);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
void cpu_dma_wbinval_range(unsigned long start, unsigned long end)
|
||
|
|
{
|
||
|
|
unsigned long line_size;
|
||
|
|
unsigned long flags;
|
||
|
|
line_size = L1_cache_info[DCACHE].line_size;
|
||
|
|
start = start & (~(line_size - 1));
|
||
|
|
end = (end + line_size - 1) & (~(line_size - 1));
|
||
|
|
if (unlikely(start == end))
|
||
|
|
return;
|
||
|
|
|
||
|
|
local_irq_save(flags);
|
||
|
|
cpu_dcache_wbinval_range(start, end);
|
||
|
|
cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_WBINVAL);
|
||
|
|
__nds32__msync_all();
|
||
|
|
local_irq_restore(flags);
|
||
|
|
}
|
||
|
|
|
||
|
|
void cpu_proc_init(void)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
void cpu_proc_fin(void)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
void cpu_do_idle(void)
|
||
|
|
{
|
||
|
|
__nds32__standby_no_wake_grant();
|
||
|
|
}
|
||
|
|
|
||
|
|
void cpu_reset(unsigned long reset)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
GIE_DISABLE();
|
||
|
|
tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL);
|
||
|
|
tmp &= ~(CACHE_CTL_mskIC_EN | CACHE_CTL_mskDC_EN);
|
||
|
|
__nds32__mtsr_isb(tmp, NDS32_SR_CACHE_CTL);
|
||
|
|
cpu_dcache_wbinval_all();
|
||
|
|
cpu_icache_inval_all();
|
||
|
|
|
||
|
|
__asm__ __volatile__("jr.toff %0\n\t"::"r"(reset));
|
||
|
|
}
|
||
|
|
|
||
|
|
void cpu_switch_mm(struct mm_struct *mm)
|
||
|
|
{
|
||
|
|
unsigned long cid;
|
||
|
|
cid = __nds32__mfsr(NDS32_SR_TLB_MISC);
|
||
|
|
cid = (cid & ~TLB_MISC_mskCID) | mm->context.id;
|
||
|
|
__nds32__mtsr_dsb(cid, NDS32_SR_TLB_MISC);
|
||
|
|
__nds32__mtsr_isb(__pa(mm->pgd), NDS32_SR_L1_PPTB);
|
||
|
|
}
|