132 lines
2.2 KiB
ArmAsm
132 lines
2.2 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2017 Andes Technology Corporation */
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#include <asm/memory.h>
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.data
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.global sp_tmp
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sp_tmp:
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.long
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.text
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.globl suspend2ram
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.globl cpu_resume
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suspend2ram:
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pushm $r0, $r31
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#if defined(CONFIG_HWZOL)
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mfusr $r0, $lc
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mfusr $r1, $le
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mfusr $r2, $lb
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#endif
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mfsr $r3, $mr0
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mfsr $r4, $mr1
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mfsr $r5, $mr4
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mfsr $r6, $mr6
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mfsr $r7, $mr7
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mfsr $r8, $mr8
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mfsr $r9, $ir0
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mfsr $r10, $ir1
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mfsr $r11, $ir2
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mfsr $r12, $ir3
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mfsr $r13, $ir9
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mfsr $r14, $ir10
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mfsr $r15, $ir12
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mfsr $r16, $ir13
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mfsr $r17, $ir14
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mfsr $r18, $ir15
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pushm $r0, $r19
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#if defined(CONFIG_FPU)
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jal store_fpu_for_suspend
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#endif
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tlbop FlushAll
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isb
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// transfer $sp from va to pa
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sethi $r0, hi20(PAGE_OFFSET)
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ori $r0, $r0, lo12(PAGE_OFFSET)
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movi $r2, PHYS_OFFSET
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sub $r1, $sp, $r0
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add $r2, $r1, $r2
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// store pa($sp) to sp_tmp
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sethi $r1, hi20(sp_tmp)
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swi $r2, [$r1 + lo12(sp_tmp)]
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pushm $r16, $r25
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pushm $r29, $r30
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#ifdef CONFIG_CACHE_L2
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jal dcache_wb_all_level
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#else
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jal cpu_dcache_wb_all
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#endif
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popm $r29, $r30
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popm $r16, $r25
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// get wake_mask and loop in standby
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la $r1, wake_mask
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lwi $r1, [$r1]
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self_loop:
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standby wake_grant
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mfsr $r2, $ir15
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and $r2, $r1, $r2
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beqz $r2, self_loop
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// set ipc to resume address
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la $r1, resume_addr
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lwi $r1, [$r1]
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mtsr $r1, $ipc
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isb
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// reset psw, turn off the address translation
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li $r2, 0x7000a
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mtsr $r2, $ipsw
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isb
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iret
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cpu_resume:
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// translate the address of sp_tmp variable to pa
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la $r1, sp_tmp
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sethi $r0, hi20(PAGE_OFFSET)
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ori $r0, $r0, lo12(PAGE_OFFSET)
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movi $r2, PHYS_OFFSET
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sub $r1, $r1, $r0
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add $r1, $r1, $r2
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// access the sp_tmp to get stack pointer
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lwi $sp, [$r1]
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popm $r0, $r19
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#if defined(CONFIG_HWZOL)
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mtusr $r0, $lb
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mtusr $r1, $lc
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mtusr $r2, $le
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#endif
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mtsr $r3, $mr0
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mtsr $r4, $mr1
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mtsr $r5, $mr4
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mtsr $r6, $mr6
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mtsr $r7, $mr7
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mtsr $r8, $mr8
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// set original psw to ipsw
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mtsr $r9, $ir1
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mtsr $r11, $ir2
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mtsr $r12, $ir3
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// set ipc to RR
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la $r13, RR
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mtsr $r13, $ir9
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mtsr $r14, $ir10
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mtsr $r15, $ir12
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mtsr $r16, $ir13
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mtsr $r17, $ir14
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mtsr $r18, $ir15
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popm $r0, $r31
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isb
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iret
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RR:
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ret
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