82 lines
2.0 KiB
C
82 lines
2.0 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* Loongson 1 Clock Register Definitions.
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*/
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#ifndef __ASM_MACH_LOONGSON32_REGS_CLK_H
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#define __ASM_MACH_LOONGSON32_REGS_CLK_H
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#define LS1X_CLK_REG(x) \
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((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))
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#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0)
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#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4)
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#if defined(CONFIG_LOONGSON1_LS1B)
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/* Clock PLL Divisor Register Bits */
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#define DIV_DC_EN BIT(31)
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#define DIV_DC_RST BIT(30)
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#define DIV_CPU_EN BIT(25)
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#define DIV_CPU_RST BIT(24)
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#define DIV_DDR_EN BIT(19)
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#define DIV_DDR_RST BIT(18)
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#define RST_DC_EN BIT(5)
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#define RST_DC BIT(4)
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#define RST_DDR_EN BIT(3)
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#define RST_DDR BIT(2)
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#define RST_CPU_EN BIT(1)
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#define RST_CPU BIT(0)
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#define DIV_DC_SHIFT 26
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#define DIV_CPU_SHIFT 20
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#define DIV_DDR_SHIFT 14
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#define DIV_DC_WIDTH 4
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#define DIV_CPU_WIDTH 4
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#define DIV_DDR_WIDTH 4
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#define BYPASS_DC_SHIFT 12
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#define BYPASS_DDR_SHIFT 10
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#define BYPASS_CPU_SHIFT 8
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#define BYPASS_DC_WIDTH 1
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#define BYPASS_DDR_WIDTH 1
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#define BYPASS_CPU_WIDTH 1
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#elif defined(CONFIG_LOONGSON1_LS1C)
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/* PLL/SDRAM Frequency configuration register Bits */
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#define PLL_VALID BIT(31)
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#define FRAC_N GENMASK(23, 16)
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#define RST_TIME GENMASK(3, 2)
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#define SDRAM_DIV GENMASK(1, 0)
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/* CPU/CAMERA/DC Frequency configuration register Bits */
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#define DIV_DC_EN BIT(31)
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#define DIV_DC GENMASK(30, 24)
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#define DIV_CAM_EN BIT(23)
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#define DIV_CAM GENMASK(22, 16)
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#define DIV_CPU_EN BIT(15)
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#define DIV_CPU GENMASK(14, 8)
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#define DIV_DC_SEL_EN BIT(5)
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#define DIV_DC_SEL BIT(4)
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#define DIV_CAM_SEL_EN BIT(3)
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#define DIV_CAM_SEL BIT(2)
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#define DIV_CPU_SEL_EN BIT(1)
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#define DIV_CPU_SEL BIT(0)
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#define DIV_DC_SHIFT 24
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#define DIV_CAM_SHIFT 16
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#define DIV_CPU_SHIFT 8
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#define DIV_DDR_SHIFT 0
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#define DIV_DC_WIDTH 7
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#define DIV_CAM_WIDTH 7
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#define DIV_CPU_WIDTH 7
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#define DIV_DDR_WIDTH 2
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#endif
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#endif /* __ASM_MACH_LOONGSON32_REGS_CLK_H */
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