81 lines
2.0 KiB
C
81 lines
2.0 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004 Cavium Networks
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*/
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#ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
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#include <linux/types.h>
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#include <asm/mipsregs.h>
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/*
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* Cavium Octeons are MIPS64v2 processors
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*/
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#define cpu_dcache_line_size() 128
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#define cpu_icache_line_size() 128
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#define cpu_has_4kex 1
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#define cpu_has_3k_cache 0
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#define cpu_has_4k_cache 0
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#define cpu_has_tx39_cache 0
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#define cpu_has_counter 1
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#define cpu_has_watch 1
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#define cpu_has_divec 1
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#define cpu_has_vce 0
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#define cpu_has_cache_cdex_p 0
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#define cpu_has_cache_cdex_s 0
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#define cpu_has_prefetch 1
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#define cpu_has_llsc 1
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/*
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* We Disable LL/SC on non SMP systems as it is faster to disable
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* interrupts for atomic access than a LL/SC.
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*/
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#ifdef CONFIG_SMP
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# define kernel_uses_llsc 1
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#else
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# define kernel_uses_llsc 0
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#endif
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#define cpu_has_vtag_icache 1
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#define cpu_has_dc_aliases 0
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#define cpu_has_ic_fills_f_dc 0
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#define cpu_has_64bits 1
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#define cpu_has_octeon_cache 1
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#define cpu_has_mips32r1 1
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#define cpu_has_mips32r2 1
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#define cpu_has_mips64r1 1
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#define cpu_has_mips64r2 1
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#define cpu_has_dsp 0
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#define cpu_has_dsp2 0
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#define cpu_has_mipsmt 0
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#define cpu_has_vint 0
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#define cpu_has_veic 0
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#define cpu_hwrena_impl_bits (MIPS_HWRENA_IMPL1 | MIPS_HWRENA_IMPL2)
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#define cpu_has_wsbh 1
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#define cpu_has_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
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#define ARCH_HAS_SPINLOCK_PREFETCH 1
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#define spin_lock_prefetch(x) prefetch(x)
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#define PREFETCH_STRIDE 128
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#ifdef __OCTEON__
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/*
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* All gcc versions that have OCTEON support define __OCTEON__ and have the
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* __builtin_popcount support.
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*/
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#define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1
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#endif
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/*
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* The last 256MB are reserved for device to device mappings and the
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* BAR1 hole.
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*/
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#define MAX_DMA32_PFN (((1ULL << 32) - (1ULL << 28)) >> PAGE_SHIFT)
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#endif
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