533 lines
14 KiB
C
533 lines
14 KiB
C
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/*
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* GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
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*
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* Copyright (c) 2009 Manuel Lauss.
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*
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* Licensed under the terms outlined in the file COPYING.
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*/
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#ifndef _ALCHEMY_GPIO_AU1000_H_
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#define _ALCHEMY_GPIO_AU1000_H_
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#include <asm/mach-au1x00/au1000.h>
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/* The default GPIO numberspace as documented in the Alchemy manuals.
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* GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
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*/
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#define ALCHEMY_GPIO1_BASE 0
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#define ALCHEMY_GPIO2_BASE 200
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#define ALCHEMY_GPIO1_NUM 32
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#define ALCHEMY_GPIO2_NUM 16
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#define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
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#define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
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#define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))
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/* GPIO1 registers within SYS_ area */
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#define AU1000_SYS_TRIOUTRD 0x100
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#define AU1000_SYS_TRIOUTCLR 0x100
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#define AU1000_SYS_OUTPUTRD 0x108
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#define AU1000_SYS_OUTPUTSET 0x108
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#define AU1000_SYS_OUTPUTCLR 0x10C
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#define AU1000_SYS_PINSTATERD 0x110
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#define AU1000_SYS_PININPUTEN 0x110
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/* register offsets within GPIO2 block */
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#define AU1000_GPIO2_DIR 0x00
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#define AU1000_GPIO2_OUTPUT 0x08
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#define AU1000_GPIO2_PINSTATE 0x0C
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#define AU1000_GPIO2_INTENABLE 0x10
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#define AU1000_GPIO2_ENABLE 0x14
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struct gpio;
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static inline int au1000_gpio1_to_irq(int gpio)
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{
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return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
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}
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static inline int au1000_gpio2_to_irq(int gpio)
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{
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return -ENXIO;
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}
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static inline int au1000_irq_to_gpio(int irq)
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{
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if ((irq >= AU1000_GPIO0_INT) && (irq <= AU1000_GPIO31_INT))
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return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0;
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return -ENXIO;
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}
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static inline int au1500_gpio1_to_irq(int gpio)
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{
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gpio -= ALCHEMY_GPIO1_BASE;
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switch (gpio) {
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case 0 ... 15:
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case 20:
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case 23 ... 28: return MAKE_IRQ(1, gpio);
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}
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return -ENXIO;
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}
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static inline int au1500_gpio2_to_irq(int gpio)
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{
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gpio -= ALCHEMY_GPIO2_BASE;
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switch (gpio) {
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case 0 ... 3: return MAKE_IRQ(1, 16 + gpio - 0);
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case 4 ... 5: return MAKE_IRQ(1, 21 + gpio - 4);
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case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
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}
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return -ENXIO;
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}
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static inline int au1500_irq_to_gpio(int irq)
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{
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switch (irq) {
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case AU1500_GPIO0_INT ... AU1500_GPIO15_INT:
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case AU1500_GPIO20_INT:
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case AU1500_GPIO23_INT ... AU1500_GPIO28_INT:
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return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0;
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case AU1500_GPIO200_INT ... AU1500_GPIO203_INT:
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return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0;
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case AU1500_GPIO204_INT ... AU1500_GPIO205_INT:
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return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4;
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case AU1500_GPIO206_INT ... AU1500_GPIO207_INT:
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return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6;
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case AU1500_GPIO208_215_INT:
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return ALCHEMY_GPIO2_BASE + 8;
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}
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return -ENXIO;
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}
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static inline int au1100_gpio1_to_irq(int gpio)
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{
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return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
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}
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static inline int au1100_gpio2_to_irq(int gpio)
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{
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gpio -= ALCHEMY_GPIO2_BASE;
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if ((gpio >= 8) && (gpio <= 15))
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return MAKE_IRQ(0, 29); /* shared GPIO208_215 */
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return -ENXIO;
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}
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static inline int au1100_irq_to_gpio(int irq)
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{
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switch (irq) {
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case AU1100_GPIO0_INT ... AU1100_GPIO31_INT:
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return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0;
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case AU1100_GPIO208_215_INT:
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return ALCHEMY_GPIO2_BASE + 8;
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}
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return -ENXIO;
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}
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static inline int au1550_gpio1_to_irq(int gpio)
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{
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gpio -= ALCHEMY_GPIO1_BASE;
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switch (gpio) {
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case 0 ... 15:
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case 20 ... 28: return MAKE_IRQ(1, gpio);
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case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);
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}
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return -ENXIO;
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}
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static inline int au1550_gpio2_to_irq(int gpio)
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{
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gpio -= ALCHEMY_GPIO2_BASE;
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switch (gpio) {
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case 0: return MAKE_IRQ(1, 16);
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case 1 ... 5: return MAKE_IRQ(1, 17); /* shared GPIO201_205 */
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case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
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case 8 ... 15: return MAKE_IRQ(1, 31); /* shared GPIO208_215 */
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}
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return -ENXIO;
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}
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static inline int au1550_irq_to_gpio(int irq)
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{
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switch (irq) {
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case AU1550_GPIO0_INT ... AU1550_GPIO15_INT:
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return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0;
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case AU1550_GPIO200_INT:
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case AU1550_GPIO201_205_INT:
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return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0;
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case AU1550_GPIO16_INT ... AU1550_GPIO28_INT:
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return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16;
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case AU1550_GPIO206_INT ... AU1550_GPIO208_215_INT:
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return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6;
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}
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return -ENXIO;
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}
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static inline int au1200_gpio1_to_irq(int gpio)
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{
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return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
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}
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static inline int au1200_gpio2_to_irq(int gpio)
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{
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gpio -= ALCHEMY_GPIO2_BASE;
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switch (gpio) {
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case 0 ... 2: return MAKE_IRQ(0, 5 + gpio - 0);
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case 3: return MAKE_IRQ(0, 22);
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case 4 ... 7: return MAKE_IRQ(0, 24 + gpio - 4);
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case 8 ... 15: return MAKE_IRQ(0, 28); /* shared GPIO208_215 */
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}
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return -ENXIO;
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}
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static inline int au1200_irq_to_gpio(int irq)
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{
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switch (irq) {
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case AU1200_GPIO0_INT ... AU1200_GPIO31_INT:
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return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0;
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case AU1200_GPIO200_INT ... AU1200_GPIO202_INT:
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return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0;
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case AU1200_GPIO203_INT:
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return ALCHEMY_GPIO2_BASE + 3;
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case AU1200_GPIO204_INT ... AU1200_GPIO208_215_INT:
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return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4;
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}
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return -ENXIO;
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}
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/*
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* GPIO1 block macros for common linux gpio functions.
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*/
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static inline void alchemy_gpio1_set_value(int gpio, int v)
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{
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unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
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unsigned long r = v ? AU1000_SYS_OUTPUTSET : AU1000_SYS_OUTPUTCLR;
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alchemy_wrsys(mask, r);
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}
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static inline int alchemy_gpio1_get_value(int gpio)
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{
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unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
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return alchemy_rdsys(AU1000_SYS_PINSTATERD) & mask;
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}
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static inline int alchemy_gpio1_direction_input(int gpio)
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{
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unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
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alchemy_wrsys(mask, AU1000_SYS_TRIOUTCLR);
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return 0;
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}
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static inline int alchemy_gpio1_direction_output(int gpio, int v)
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{
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/* hardware switches to "output" mode when one of the two
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* "set_value" registers is accessed.
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*/
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alchemy_gpio1_set_value(gpio, v);
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return 0;
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}
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static inline int alchemy_gpio1_is_valid(int gpio)
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{
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return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX));
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}
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static inline int alchemy_gpio1_to_irq(int gpio)
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{
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switch (alchemy_get_cputype()) {
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case ALCHEMY_CPU_AU1000:
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return au1000_gpio1_to_irq(gpio);
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case ALCHEMY_CPU_AU1100:
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return au1100_gpio1_to_irq(gpio);
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case ALCHEMY_CPU_AU1500:
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return au1500_gpio1_to_irq(gpio);
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case ALCHEMY_CPU_AU1550:
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return au1550_gpio1_to_irq(gpio);
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case ALCHEMY_CPU_AU1200:
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return au1200_gpio1_to_irq(gpio);
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}
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return -ENXIO;
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}
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/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
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* SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this
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* register enables use of GPIOs as wake source.
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*/
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static inline void alchemy_gpio1_input_enable(void)
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{
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void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
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__raw_writel(0, base + 0x110); /* the write op is key */
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wmb();
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}
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/*
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* GPIO2 block macros for common linux GPIO functions. The 'gpio'
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* parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX.
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*/
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static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
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{
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void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
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unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
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unsigned long d = __raw_readl(base + AU1000_GPIO2_DIR);
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if (to_out)
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d |= mask;
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else
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d &= ~mask;
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__raw_writel(d, base + AU1000_GPIO2_DIR);
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wmb();
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}
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static inline void alchemy_gpio2_set_value(int gpio, int v)
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{
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void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
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unsigned long mask;
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mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
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__raw_writel(mask, base + AU1000_GPIO2_OUTPUT);
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wmb();
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}
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static inline int alchemy_gpio2_get_value(int gpio)
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{
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void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
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return __raw_readl(base + AU1000_GPIO2_PINSTATE) &
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(1 << (gpio - ALCHEMY_GPIO2_BASE));
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}
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static inline int alchemy_gpio2_direction_input(int gpio)
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{
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unsigned long flags;
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local_irq_save(flags);
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__alchemy_gpio2_mod_dir(gpio, 0);
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local_irq_restore(flags);
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return 0;
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}
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static inline int alchemy_gpio2_direction_output(int gpio, int v)
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{
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unsigned long flags;
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alchemy_gpio2_set_value(gpio, v);
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local_irq_save(flags);
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__alchemy_gpio2_mod_dir(gpio, 1);
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local_irq_restore(flags);
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return 0;
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}
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static inline int alchemy_gpio2_is_valid(int gpio)
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{
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return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX));
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}
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static inline int alchemy_gpio2_to_irq(int gpio)
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{
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switch (alchemy_get_cputype()) {
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case ALCHEMY_CPU_AU1000:
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return au1000_gpio2_to_irq(gpio);
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case ALCHEMY_CPU_AU1100:
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return au1100_gpio2_to_irq(gpio);
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case ALCHEMY_CPU_AU1500:
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return au1500_gpio2_to_irq(gpio);
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case ALCHEMY_CPU_AU1550:
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return au1550_gpio2_to_irq(gpio);
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case ALCHEMY_CPU_AU1200:
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return au1200_gpio2_to_irq(gpio);
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}
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return -ENXIO;
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}
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/**********************************************************************/
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/* GPIO2 shared interrupts and control */
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static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
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{
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|
|
void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
|
||
|
|
unsigned long r = __raw_readl(base + AU1000_GPIO2_INTENABLE);
|
||
|
|
if (en)
|
||
|
|
r |= 1 << gpio2;
|
||
|
|
else
|
||
|
|
r &= ~(1 << gpio2);
|
||
|
|
__raw_writel(r, base + AU1000_GPIO2_INTENABLE);
|
||
|
|
wmb();
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution.
|
||
|
|
* @gpio2: The GPIO2 pin to activate (200...215).
|
||
|
|
*
|
||
|
|
* GPIO208-215 have one shared interrupt line to the INTC. They are
|
||
|
|
* and'ed with a per-pin enable bit and finally or'ed together to form
|
||
|
|
* a single irq request (useful for active-high sources).
|
||
|
|
* With this function, a pins' individual contribution to the int request
|
||
|
|
* can be enabled. As with all other GPIO-based interrupts, the INTC
|
||
|
|
* must be programmed to accept the GPIO208_215 interrupt as well.
|
||
|
|
*
|
||
|
|
* NOTE: Calling this macro is only necessary for GPIO208-215; all other
|
||
|
|
* GPIO2-based interrupts have their own request to the INTC. Please
|
||
|
|
* consult your Alchemy databook for more information!
|
||
|
|
*
|
||
|
|
* NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request
|
||
|
|
* line to the INTC, GPIO201_205. This function can be used for those
|
||
|
|
* as well.
|
||
|
|
*
|
||
|
|
* NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace
|
||
|
|
* (200-215 by default). No sanity checks are made,
|
||
|
|
*/
|
||
|
|
static inline void alchemy_gpio2_enable_int(int gpio2)
|
||
|
|
{
|
||
|
|
unsigned long flags;
|
||
|
|
|
||
|
|
gpio2 -= ALCHEMY_GPIO2_BASE;
|
||
|
|
|
||
|
|
/* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
|
||
|
|
switch (alchemy_get_cputype()) {
|
||
|
|
case ALCHEMY_CPU_AU1100:
|
||
|
|
case ALCHEMY_CPU_AU1500:
|
||
|
|
gpio2 -= 8;
|
||
|
|
}
|
||
|
|
|
||
|
|
local_irq_save(flags);
|
||
|
|
__alchemy_gpio2_mod_int(gpio2, 1);
|
||
|
|
local_irq_restore(flags);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution.
|
||
|
|
* @gpio2: The GPIO2 pin to activate (200...215).
|
||
|
|
*
|
||
|
|
* see function alchemy_gpio2_enable_int() for more information.
|
||
|
|
*/
|
||
|
|
static inline void alchemy_gpio2_disable_int(int gpio2)
|
||
|
|
{
|
||
|
|
unsigned long flags;
|
||
|
|
|
||
|
|
gpio2 -= ALCHEMY_GPIO2_BASE;
|
||
|
|
|
||
|
|
/* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
|
||
|
|
switch (alchemy_get_cputype()) {
|
||
|
|
case ALCHEMY_CPU_AU1100:
|
||
|
|
case ALCHEMY_CPU_AU1500:
|
||
|
|
gpio2 -= 8;
|
||
|
|
}
|
||
|
|
|
||
|
|
local_irq_save(flags);
|
||
|
|
__alchemy_gpio2_mod_int(gpio2, 0);
|
||
|
|
local_irq_restore(flags);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* alchemy_gpio2_enable - Activate GPIO2 block.
|
||
|
|
*
|
||
|
|
* The GPIO2 block must be enabled excplicitly to work. On systems
|
||
|
|
* where this isn't done by the bootloader, this macro can be used.
|
||
|
|
*/
|
||
|
|
static inline void alchemy_gpio2_enable(void)
|
||
|
|
{
|
||
|
|
void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
|
||
|
|
__raw_writel(3, base + AU1000_GPIO2_ENABLE); /* reset, clock enabled */
|
||
|
|
wmb();
|
||
|
|
__raw_writel(1, base + AU1000_GPIO2_ENABLE); /* clock enabled */
|
||
|
|
wmb();
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* alchemy_gpio2_disable - disable GPIO2 block.
|
||
|
|
*
|
||
|
|
* Disable and put GPIO2 block in low-power mode.
|
||
|
|
*/
|
||
|
|
static inline void alchemy_gpio2_disable(void)
|
||
|
|
{
|
||
|
|
void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
|
||
|
|
__raw_writel(2, base + AU1000_GPIO2_ENABLE); /* reset, clock disabled */
|
||
|
|
wmb();
|
||
|
|
}
|
||
|
|
|
||
|
|
/**********************************************************************/
|
||
|
|
|
||
|
|
/* wrappers for on-chip gpios; can be used before gpio chips have been
|
||
|
|
* registered with gpiolib.
|
||
|
|
*/
|
||
|
|
static inline int alchemy_gpio_direction_input(int gpio)
|
||
|
|
{
|
||
|
|
return (gpio >= ALCHEMY_GPIO2_BASE) ?
|
||
|
|
alchemy_gpio2_direction_input(gpio) :
|
||
|
|
alchemy_gpio1_direction_input(gpio);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int alchemy_gpio_direction_output(int gpio, int v)
|
||
|
|
{
|
||
|
|
return (gpio >= ALCHEMY_GPIO2_BASE) ?
|
||
|
|
alchemy_gpio2_direction_output(gpio, v) :
|
||
|
|
alchemy_gpio1_direction_output(gpio, v);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int alchemy_gpio_get_value(int gpio)
|
||
|
|
{
|
||
|
|
return (gpio >= ALCHEMY_GPIO2_BASE) ?
|
||
|
|
alchemy_gpio2_get_value(gpio) :
|
||
|
|
alchemy_gpio1_get_value(gpio);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void alchemy_gpio_set_value(int gpio, int v)
|
||
|
|
{
|
||
|
|
if (gpio >= ALCHEMY_GPIO2_BASE)
|
||
|
|
alchemy_gpio2_set_value(gpio, v);
|
||
|
|
else
|
||
|
|
alchemy_gpio1_set_value(gpio, v);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int alchemy_gpio_is_valid(int gpio)
|
||
|
|
{
|
||
|
|
return (gpio >= ALCHEMY_GPIO2_BASE) ?
|
||
|
|
alchemy_gpio2_is_valid(gpio) :
|
||
|
|
alchemy_gpio1_is_valid(gpio);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int alchemy_gpio_cansleep(int gpio)
|
||
|
|
{
|
||
|
|
return 0; /* Alchemy never gets tired */
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int alchemy_gpio_to_irq(int gpio)
|
||
|
|
{
|
||
|
|
return (gpio >= ALCHEMY_GPIO2_BASE) ?
|
||
|
|
alchemy_gpio2_to_irq(gpio) :
|
||
|
|
alchemy_gpio1_to_irq(gpio);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int alchemy_irq_to_gpio(int irq)
|
||
|
|
{
|
||
|
|
switch (alchemy_get_cputype()) {
|
||
|
|
case ALCHEMY_CPU_AU1000:
|
||
|
|
return au1000_irq_to_gpio(irq);
|
||
|
|
case ALCHEMY_CPU_AU1100:
|
||
|
|
return au1100_irq_to_gpio(irq);
|
||
|
|
case ALCHEMY_CPU_AU1500:
|
||
|
|
return au1500_irq_to_gpio(irq);
|
||
|
|
case ALCHEMY_CPU_AU1550:
|
||
|
|
return au1550_irq_to_gpio(irq);
|
||
|
|
case ALCHEMY_CPU_AU1200:
|
||
|
|
return au1200_irq_to_gpio(irq);
|
||
|
|
}
|
||
|
|
return -ENXIO;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* _ALCHEMY_GPIO_AU1000_H_ */
|