198 lines
5.4 KiB
C
198 lines
5.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/***************************************************************************/
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/*
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* m520x.c -- platform support for ColdFire 520x based boards
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*
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* Copyright (C) 2005, Freescale (www.freescale.com)
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* Copyright (C) 2005, Intec Automation (mike@steroidmicros.com)
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* Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfuart.h>
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#include <asm/mcfclk.h>
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/***************************************************************************/
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DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
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DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
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DEFINE_CLK(0, "edma", 17, MCF_CLK);
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DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
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DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
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DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
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DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
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DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
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DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
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DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
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DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
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DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
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DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
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DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
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DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
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DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
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DEFINE_CLK(0, "mcfeport.0", 34, MCF_CLK);
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DEFINE_CLK(0, "mcfwdt.0", 35, MCF_CLK);
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DEFINE_CLK(0, "pll.0", 36, MCF_CLK);
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DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
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DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
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DEFINE_CLK(0, "sdram.0", 42, MCF_CLK);
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struct clk *mcf_clks[] = {
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&__clk_0_2, /* flexbus */
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&__clk_0_12, /* fec.0 */
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&__clk_0_17, /* edma */
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&__clk_0_18, /* intc.0 */
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&__clk_0_21, /* iack.0 */
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&__clk_0_22, /* imx1-i2c.0 */
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&__clk_0_23, /* mcfqspi.0 */
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&__clk_0_24, /* mcfuart.0 */
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&__clk_0_25, /* mcfuart.1 */
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&__clk_0_26, /* mcfuart.2 */
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&__clk_0_28, /* mcftmr.0 */
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&__clk_0_29, /* mcftmr.1 */
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&__clk_0_30, /* mcftmr.2 */
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&__clk_0_31, /* mcftmr.3 */
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&__clk_0_32, /* mcfpit.0 */
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&__clk_0_33, /* mcfpit.1 */
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&__clk_0_34, /* mcfeport.0 */
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&__clk_0_35, /* mcfwdt.0 */
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&__clk_0_36, /* pll.0 */
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&__clk_0_40, /* sys.0 */
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&__clk_0_41, /* gpio.0 */
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&__clk_0_42, /* sdram.0 */
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NULL,
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};
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static struct clk * const enable_clks[] __initconst = {
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&__clk_0_2, /* flexbus */
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&__clk_0_18, /* intc.0 */
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&__clk_0_21, /* iack.0 */
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&__clk_0_24, /* mcfuart.0 */
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&__clk_0_25, /* mcfuart.1 */
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&__clk_0_26, /* mcfuart.2 */
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&__clk_0_32, /* mcfpit.0 */
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&__clk_0_33, /* mcfpit.1 */
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&__clk_0_34, /* mcfeport.0 */
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&__clk_0_36, /* pll.0 */
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&__clk_0_40, /* sys.0 */
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&__clk_0_41, /* gpio.0 */
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&__clk_0_42, /* sdram.0 */
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};
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static struct clk * const disable_clks[] __initconst = {
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&__clk_0_12, /* fec.0 */
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&__clk_0_17, /* edma */
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&__clk_0_22, /* imx1-i2c.0 */
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&__clk_0_23, /* mcfqspi.0 */
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&__clk_0_28, /* mcftmr.0 */
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&__clk_0_29, /* mcftmr.1 */
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&__clk_0_30, /* mcftmr.2 */
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&__clk_0_31, /* mcftmr.3 */
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&__clk_0_35, /* mcfwdt.0 */
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};
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static void __init m520x_clk_init(void)
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{
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unsigned i;
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/* make sure these clocks are enabled */
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for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
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__clk_init_enabled(enable_clks[i]);
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/* make sure these clocks are disabled */
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for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
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__clk_init_disabled(disable_clks[i]);
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}
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/***************************************************************************/
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static void __init m520x_qspi_init(void)
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{
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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u16 par;
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/* setup Port QS for QSPI with gpio CS control */
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writeb(0x3f, MCF_GPIO_PAR_QSPI);
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/* make U1CTS and U2RTS gpio for cs_control */
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par = readw(MCF_GPIO_PAR_UART);
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par &= 0x00ff;
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writew(par, MCF_GPIO_PAR_UART);
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#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
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}
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/***************************************************************************/
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static void __init m520x_i2c_init(void)
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{
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#if IS_ENABLED(CONFIG_I2C_IMX)
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u8 par;
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/* setup Port FECI2C Pin Assignment Register for I2C */
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/* set PAR_SCL to SCL and PAR_SDA to SDA */
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par = readb(MCF_GPIO_PAR_FECI2C);
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par |= 0x0f;
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writeb(par, MCF_GPIO_PAR_FECI2C);
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#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
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}
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/***************************************************************************/
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static void __init m520x_uarts_init(void)
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{
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u16 par;
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u8 par2;
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/* UART0 and UART1 GPIO pin setup */
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par = readw(MCF_GPIO_PAR_UART);
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par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
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par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
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writew(par, MCF_GPIO_PAR_UART);
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/* UART1 GPIO pin setup */
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par2 = readb(MCF_GPIO_PAR_FECI2C);
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par2 &= ~0x0F;
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par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
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MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
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writeb(par2, MCF_GPIO_PAR_FECI2C);
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}
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/***************************************************************************/
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static void __init m520x_fec_init(void)
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{
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u8 v;
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/* Set multi-function pins to ethernet mode */
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v = readb(MCF_GPIO_PAR_FEC);
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writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
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v = readb(MCF_GPIO_PAR_FECI2C);
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writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
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}
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/***************************************************************************/
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void __init config_BSP(char *commandp, int size)
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{
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mach_sched_init = hw_timer_init;
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m520x_clk_init();
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m520x_uarts_init();
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m520x_fec_init();
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m520x_qspi_init();
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m520x_i2c_init();
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}
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/***************************************************************************/
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