515 lines
13 KiB
C
515 lines
13 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Derived from arch/arm/include/kvm_emulate.h
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*/
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#ifndef __ARM64_KVM_EMULATE_H__
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#define __ARM64_KVM_EMULATE_H__
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#include <linux/kvm_host.h>
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#include <asm/debug-monitors.h>
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#include <asm/esr.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_hyp.h>
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#include <asm/kvm_mmio.h>
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#include <asm/ptrace.h>
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#include <asm/cputype.h>
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#include <asm/virt.h>
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unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num);
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unsigned long vcpu_read_spsr32(const struct kvm_vcpu *vcpu);
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void vcpu_write_spsr32(struct kvm_vcpu *vcpu, unsigned long v);
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bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
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void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr);
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void kvm_inject_undefined(struct kvm_vcpu *vcpu);
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void kvm_inject_vabt(struct kvm_vcpu *vcpu);
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void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_undef32(struct kvm_vcpu *vcpu);
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void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr);
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static inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
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{
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return !(vcpu->arch.hcr_el2 & HCR_RW);
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}
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static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
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if (is_kernel_in_hyp_mode())
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vcpu->arch.hcr_el2 |= HCR_E2H;
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if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN)) {
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/* route synchronous external abort exceptions to EL2 */
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vcpu->arch.hcr_el2 |= HCR_TEA;
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/* trap error record accesses */
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vcpu->arch.hcr_el2 |= HCR_TERR;
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}
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if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
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vcpu->arch.hcr_el2 |= HCR_FWB;
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if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features))
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vcpu->arch.hcr_el2 &= ~HCR_RW;
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/*
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* TID3: trap feature register accesses that we virtualise.
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* For now this is conditional, since no AArch32 feature regs
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* are currently virtualised.
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*/
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if (!vcpu_el1_is_32bit(vcpu))
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vcpu->arch.hcr_el2 |= HCR_TID3;
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if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) ||
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vcpu_el1_is_32bit(vcpu))
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vcpu->arch.hcr_el2 |= HCR_TID2;
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}
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static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu)
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{
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return (unsigned long *)&vcpu->arch.hcr_el2;
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}
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static inline void vcpu_clear_wfe_traps(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hcr_el2 &= ~HCR_TWE;
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}
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static inline void vcpu_set_wfe_traps(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hcr_el2 |= HCR_TWE;
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}
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static inline void vcpu_ptrauth_enable(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hcr_el2 |= (HCR_API | HCR_APK);
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}
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static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hcr_el2 &= ~(HCR_API | HCR_APK);
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}
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static inline void vcpu_ptrauth_setup_lazy(struct kvm_vcpu *vcpu)
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{
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if (vcpu_has_ptrauth(vcpu))
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vcpu_ptrauth_disable(vcpu);
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}
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static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.vsesr_el2;
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}
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static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr)
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{
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vcpu->arch.vsesr_el2 = vsesr;
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}
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static inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
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{
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return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;
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}
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static inline unsigned long *__vcpu_elr_el1(const struct kvm_vcpu *vcpu)
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{
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return (unsigned long *)&vcpu_gp_regs(vcpu)->elr_el1;
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}
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static inline unsigned long vcpu_read_elr_el1(const struct kvm_vcpu *vcpu)
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{
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if (vcpu->arch.sysregs_loaded_on_cpu)
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return read_sysreg_el1(SYS_ELR);
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else
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return *__vcpu_elr_el1(vcpu);
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}
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static inline void vcpu_write_elr_el1(const struct kvm_vcpu *vcpu, unsigned long v)
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{
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if (vcpu->arch.sysregs_loaded_on_cpu)
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write_sysreg_el1(v, SYS_ELR);
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else
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*__vcpu_elr_el1(vcpu) = v;
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}
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static inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
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{
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return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate;
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}
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static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
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{
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return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
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}
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static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
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{
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if (vcpu_mode_is_32bit(vcpu))
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return kvm_condition_valid32(vcpu);
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return true;
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}
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static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
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{
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*vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT;
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}
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/*
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* vcpu_get_reg and vcpu_set_reg should always be passed a register number
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* coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
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* AArch32 with banked registers.
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*/
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static inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,
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u8 reg_num)
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{
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return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs.regs[reg_num];
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}
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static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
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unsigned long val)
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{
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if (reg_num != 31)
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vcpu_gp_regs(vcpu)->regs.regs[reg_num] = val;
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}
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static inline unsigned long vcpu_read_spsr(const struct kvm_vcpu *vcpu)
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{
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if (vcpu_mode_is_32bit(vcpu))
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return vcpu_read_spsr32(vcpu);
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if (vcpu->arch.sysregs_loaded_on_cpu)
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return read_sysreg_el1(SYS_SPSR);
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else
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return vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1];
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}
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static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v)
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{
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if (vcpu_mode_is_32bit(vcpu)) {
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vcpu_write_spsr32(vcpu, v);
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return;
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}
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if (vcpu->arch.sysregs_loaded_on_cpu)
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write_sysreg_el1(v, SYS_SPSR);
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else
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vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1] = v;
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}
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/*
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* The layout of SPSR for an AArch32 state is different when observed from an
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* AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32
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* view given an AArch64 view.
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*
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* In ARM DDI 0487E.a see:
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*
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* - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426
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* - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256
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* - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280
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*
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* Which show the following differences:
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*
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* | Bit | AA64 | AA32 | Notes |
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* +-----+------+------+-----------------------------|
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* | 24 | DIT | J | J is RES0 in ARMv8 |
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* | 21 | SS | DIT | SS doesn't exist in AArch32 |
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*
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* ... and all other bits are (currently) common.
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*/
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static inline unsigned long host_spsr_to_spsr32(unsigned long spsr)
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{
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const unsigned long overlap = BIT(24) | BIT(21);
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unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT);
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spsr &= ~overlap;
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spsr |= dit << 21;
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return spsr;
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}
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static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
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{
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u32 mode;
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if (vcpu_mode_is_32bit(vcpu)) {
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mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK;
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return mode > PSR_AA32_MODE_USR;
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}
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mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
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return mode != PSR_MODE_EL0t;
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}
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static inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.fault.esr_el2;
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}
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static inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
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{
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u32 esr = kvm_vcpu_get_hsr(vcpu);
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if (esr & ESR_ELx_CV)
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return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
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return -1;
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}
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static inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.fault.far_el2;
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}
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static inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
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{
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return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
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}
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static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.fault.disr_el1;
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}
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static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_xVC_IMM_MASK;
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}
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static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
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{
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return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV);
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}
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static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
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{
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return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE);
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}
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static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu)
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{
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return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SF);
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}
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static inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
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{
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return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
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}
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static inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)
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{
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return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW);
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}
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static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
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{
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return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR) ||
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kvm_vcpu_dabt_iss1tw(vcpu); /* AF/DBM update */
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}
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static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu)
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{
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return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_CM);
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}
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static inline int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
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{
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return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
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}
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/* This one is not specific to Data Abort */
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static inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
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{
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return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_IL);
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}
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static inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
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{
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return ESR_ELx_EC(kvm_vcpu_get_hsr(vcpu));
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}
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static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
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{
|
||
|
|
return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC_TYPE;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
switch (kvm_vcpu_trap_get_fault(vcpu)) {
|
||
|
|
case FSC_SEA:
|
||
|
|
case FSC_SEA_TTW0:
|
||
|
|
case FSC_SEA_TTW1:
|
||
|
|
case FSC_SEA_TTW2:
|
||
|
|
case FSC_SEA_TTW3:
|
||
|
|
case FSC_SECC:
|
||
|
|
case FSC_SECC_TTW0:
|
||
|
|
case FSC_SECC_TTW1:
|
||
|
|
case FSC_SECC_TTW2:
|
||
|
|
case FSC_SECC_TTW3:
|
||
|
|
return true;
|
||
|
|
default:
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
u32 esr = kvm_vcpu_get_hsr(vcpu);
|
||
|
|
return ESR_ELx_SYS64_ISS_RT(esr);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
if (kvm_vcpu_trap_is_iabt(vcpu))
|
||
|
|
return false;
|
||
|
|
|
||
|
|
return kvm_vcpu_dabt_iswrite(vcpu);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
return vcpu_read_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool kvm_arm_get_vcpu_workaround_2_flag(struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
return vcpu->arch.workaround_flags & VCPU_WORKAROUND_2_FLAG;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void kvm_arm_set_vcpu_workaround_2_flag(struct kvm_vcpu *vcpu,
|
||
|
|
bool flag)
|
||
|
|
{
|
||
|
|
if (flag)
|
||
|
|
vcpu->arch.workaround_flags |= VCPU_WORKAROUND_2_FLAG;
|
||
|
|
else
|
||
|
|
vcpu->arch.workaround_flags &= ~VCPU_WORKAROUND_2_FLAG;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
if (vcpu_mode_is_32bit(vcpu)) {
|
||
|
|
*vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT;
|
||
|
|
} else {
|
||
|
|
u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);
|
||
|
|
sctlr |= (1 << 25);
|
||
|
|
vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
if (vcpu_mode_is_32bit(vcpu))
|
||
|
|
return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT);
|
||
|
|
|
||
|
|
return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & (1 << 25));
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
|
||
|
|
unsigned long data,
|
||
|
|
unsigned int len)
|
||
|
|
{
|
||
|
|
if (kvm_vcpu_is_be(vcpu)) {
|
||
|
|
switch (len) {
|
||
|
|
case 1:
|
||
|
|
return data & 0xff;
|
||
|
|
case 2:
|
||
|
|
return be16_to_cpu(data & 0xffff);
|
||
|
|
case 4:
|
||
|
|
return be32_to_cpu(data & 0xffffffff);
|
||
|
|
default:
|
||
|
|
return be64_to_cpu(data);
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
switch (len) {
|
||
|
|
case 1:
|
||
|
|
return data & 0xff;
|
||
|
|
case 2:
|
||
|
|
return le16_to_cpu(data & 0xffff);
|
||
|
|
case 4:
|
||
|
|
return le32_to_cpu(data & 0xffffffff);
|
||
|
|
default:
|
||
|
|
return le64_to_cpu(data);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return data; /* Leave LE untouched */
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
|
||
|
|
unsigned long data,
|
||
|
|
unsigned int len)
|
||
|
|
{
|
||
|
|
if (kvm_vcpu_is_be(vcpu)) {
|
||
|
|
switch (len) {
|
||
|
|
case 1:
|
||
|
|
return data & 0xff;
|
||
|
|
case 2:
|
||
|
|
return cpu_to_be16(data & 0xffff);
|
||
|
|
case 4:
|
||
|
|
return cpu_to_be32(data & 0xffffffff);
|
||
|
|
default:
|
||
|
|
return cpu_to_be64(data);
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
switch (len) {
|
||
|
|
case 1:
|
||
|
|
return data & 0xff;
|
||
|
|
case 2:
|
||
|
|
return cpu_to_le16(data & 0xffff);
|
||
|
|
case 4:
|
||
|
|
return cpu_to_le32(data & 0xffffffff);
|
||
|
|
default:
|
||
|
|
return cpu_to_le64(data);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return data; /* Leave LE untouched */
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
|
||
|
|
{
|
||
|
|
if (vcpu_mode_is_32bit(vcpu))
|
||
|
|
kvm_skip_instr32(vcpu, is_wide_instr);
|
||
|
|
else
|
||
|
|
*vcpu_pc(vcpu) += 4;
|
||
|
|
|
||
|
|
/* advance the singlestep state machine */
|
||
|
|
*vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Skip an instruction which has been emulated at hyp while most guest sysregs
|
||
|
|
* are live.
|
||
|
|
*/
|
||
|
|
static inline void __hyp_text __kvm_skip_instr(struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
*vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);
|
||
|
|
vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(SYS_SPSR);
|
||
|
|
|
||
|
|
kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
|
||
|
|
|
||
|
|
write_sysreg_el2(vcpu->arch.ctxt.gp_regs.regs.pstate, SYS_SPSR);
|
||
|
|
write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* __ARM64_KVM_EMULATE_H__ */
|