133 lines
3.2 KiB
ArmAsm
133 lines
3.2 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Scalar AES core transform
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*
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* Copyright (C) 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/cache.h>
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.text
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rk .req x0
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out .req x1
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in .req x2
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rounds .req x3
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tt .req x2
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.macro __pair1, sz, op, reg0, reg1, in0, in1e, in1d, shift
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.ifc \op\shift, b0
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ubfiz \reg0, \in0, #2, #8
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ubfiz \reg1, \in1e, #2, #8
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.else
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ubfx \reg0, \in0, #\shift, #8
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ubfx \reg1, \in1e, #\shift, #8
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.endif
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/*
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* AArch64 cannot do byte size indexed loads from a table containing
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* 32-bit quantities, i.e., 'ldrb w12, [tt, w12, uxtw #2]' is not a
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* valid instruction. So perform the shift explicitly first for the
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* high bytes (the low byte is shifted implicitly by using ubfiz rather
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* than ubfx above)
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*/
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.ifnc \op, b
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ldr \reg0, [tt, \reg0, uxtw #2]
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ldr \reg1, [tt, \reg1, uxtw #2]
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.else
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.if \shift > 0
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lsl \reg0, \reg0, #2
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lsl \reg1, \reg1, #2
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.endif
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ldrb \reg0, [tt, \reg0, uxtw]
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ldrb \reg1, [tt, \reg1, uxtw]
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.endif
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.endm
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.macro __pair0, sz, op, reg0, reg1, in0, in1e, in1d, shift
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ubfx \reg0, \in0, #\shift, #8
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ubfx \reg1, \in1d, #\shift, #8
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ldr\op \reg0, [tt, \reg0, uxtw #\sz]
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ldr\op \reg1, [tt, \reg1, uxtw #\sz]
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.endm
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.macro __hround, out0, out1, in0, in1, in2, in3, t0, t1, enc, sz, op
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ldp \out0, \out1, [rk], #8
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__pair\enc \sz, \op, w12, w13, \in0, \in1, \in3, 0
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__pair\enc \sz, \op, w14, w15, \in1, \in2, \in0, 8
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__pair\enc \sz, \op, w16, w17, \in2, \in3, \in1, 16
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__pair\enc \sz, \op, \t0, \t1, \in3, \in0, \in2, 24
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eor \out0, \out0, w12
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eor \out1, \out1, w13
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eor \out0, \out0, w14, ror #24
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eor \out1, \out1, w15, ror #24
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eor \out0, \out0, w16, ror #16
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eor \out1, \out1, w17, ror #16
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eor \out0, \out0, \t0, ror #8
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eor \out1, \out1, \t1, ror #8
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.endm
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.macro fround, out0, out1, out2, out3, in0, in1, in2, in3, sz=2, op
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__hround \out0, \out1, \in0, \in1, \in2, \in3, \out2, \out3, 1, \sz, \op
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__hround \out2, \out3, \in2, \in3, \in0, \in1, \in1, \in2, 1, \sz, \op
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.endm
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.macro iround, out0, out1, out2, out3, in0, in1, in2, in3, sz=2, op
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__hround \out0, \out1, \in0, \in3, \in2, \in1, \out2, \out3, 0, \sz, \op
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__hround \out2, \out3, \in2, \in1, \in0, \in3, \in1, \in0, 0, \sz, \op
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.endm
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.macro do_crypt, round, ttab, ltab, bsz
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ldp w4, w5, [in]
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ldp w6, w7, [in, #8]
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ldp w8, w9, [rk], #16
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ldp w10, w11, [rk, #-8]
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CPU_BE( rev w4, w4 )
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CPU_BE( rev w5, w5 )
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CPU_BE( rev w6, w6 )
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CPU_BE( rev w7, w7 )
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eor w4, w4, w8
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eor w5, w5, w9
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eor w6, w6, w10
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eor w7, w7, w11
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adr_l tt, \ttab
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tbnz rounds, #1, 1f
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0: \round w8, w9, w10, w11, w4, w5, w6, w7
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\round w4, w5, w6, w7, w8, w9, w10, w11
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1: subs rounds, rounds, #4
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\round w8, w9, w10, w11, w4, w5, w6, w7
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b.ls 3f
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2: \round w4, w5, w6, w7, w8, w9, w10, w11
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b 0b
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3: adr_l tt, \ltab
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\round w4, w5, w6, w7, w8, w9, w10, w11, \bsz, b
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CPU_BE( rev w4, w4 )
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CPU_BE( rev w5, w5 )
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CPU_BE( rev w6, w6 )
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CPU_BE( rev w7, w7 )
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stp w4, w5, [out]
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stp w6, w7, [out, #8]
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ret
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.endm
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ENTRY(__aes_arm64_encrypt)
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do_crypt fround, crypto_ft_tab, crypto_ft_tab + 1, 2
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ENDPROC(__aes_arm64_encrypt)
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.align 5
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ENTRY(__aes_arm64_decrypt)
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do_crypt iround, crypto_it_tab, crypto_aes_inv_sbox, 0
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ENDPROC(__aes_arm64_decrypt)
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