first version

This commit is contained in:
chenyf 2023-01-07 23:34:23 +08:00
commit b605c6f22b
156 changed files with 58646 additions and 0 deletions

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{
"files.associations": {
"hk32f030m.h": "c"
}
}

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<?xml version="1.0" encoding="utf-8"?>
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
<events>
</events>
</component_viewer>

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Project/JLinkLog.txt Normal file

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[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 1
Device="Cortex-M0"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

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Component: ARM Compiler 5.06 update 3 (build 300) Tool: armlink [4d35c9]
==============================================================================
Section Cross References
main.o(i.main) refers to bsp_led.o(i.LED_GPIO_Config) for LED_GPIO_Config
bsp_led.o(i.LED_GPIO_Config) refers to hk32f030m_rcc.o(i.RCC_AHBPeriphClockCmd) for RCC_AHBPeriphClockCmd
bsp_led.o(i.LED_GPIO_Config) refers to hk32f030m_gpio.o(i.GPIO_Init) for GPIO_Init
bsp_led.o(i.LED_GPIO_Config) refers to hk32f030m_gpio.o(i.GPIO_SetBits) for GPIO_SetBits
hk32f030m_adc.o(i.ADC_DeInit) refers to hk32f030m_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
hk32f030m_flash.o(i.EEPROM_EraseByte) refers to hk32f030m_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
hk32f030m_flash.o(i.EEPROM_ProgramByte) refers to hk32f030m_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
hk32f030m_flash.o(i.FLASH_EraseAllPages) refers to hk32f030m_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
hk32f030m_flash.o(i.FLASH_ErasePage) refers to hk32f030m_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
hk32f030m_flash.o(i.FLASH_OB_DBGCLKConfig) refers to hk32f030m_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
hk32f030m_flash.o(i.FLASH_OB_EraseByte) refers to hk32f030m_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
hk32f030m_flash.o(i.FLASH_OB_IWDG_RLRConfig) refers to hk32f030m_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
hk32f030m_flash.o(i.FLASH_OB_LSILPConfig) refers to hk32f030m_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
hk32f030m_flash.o(i.FLASH_OB_ProgramData) refers to hk32f030m_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
hk32f030m_flash.o(i.FLASH_OB_RDPConfig) refers to hk32f030m_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
hk32f030m_flash.o(i.FLASH_OB_UserConfig) refers to hk32f030m_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
hk32f030m_flash.o(i.FLASH_OB_WRPConfig) refers to hk32f030m_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
hk32f030m_flash.o(i.FLASH_OB_WriteUser) refers to hk32f030m_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
hk32f030m_flash.o(i.FLASH_ProgramByte) refers to hk32f030m_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
hk32f030m_flash.o(i.FLASH_ProgramHalfWord) refers to hk32f030m_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
hk32f030m_flash.o(i.FLASH_WaitForLastOperation) refers to hk32f030m_flash.o(i.FLASH_GetStatus) for FLASH_GetStatus
hk32f030m_gpio.o(i.GPIO_DeInit) refers to hk32f030m_rcc.o(i.RCC_AHBPeriphResetCmd) for RCC_AHBPeriphResetCmd
hk32f030m_gpio.o(i.GPIO_IOMUX_ChangePin) refers to hk32f030m_gpio.o(i.__ARM_common_switch8) for __ARM_common_switch8
hk32f030m_i2c.o(i.I2C_DeInit) refers to hk32f030m_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd
hk32f030m_pwr.o(i.PWR_DeInit) refers to hk32f030m_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd
hk32f030m_pwr.o(i.PWR_EnterDeepSleepMode) refers to hk32f030m_pwr.o(i.Sysclk_SwitchToLSI) for Sysclk_SwitchToLSI
hk32f030m_pwr.o(i.PWR_EnterDeepSleepMode) refers to hk32f030m_pwr.o(i.PWR_EnterSleepMode) for PWR_EnterSleepMode
hk32f030m_pwr.o(i.PWR_EnterStopMode) refers to hk32f030m_exti.o(i.EXTI_GetFlagStatus) for EXTI_GetFlagStatus
hk32f030m_pwr.o(i.PWR_EnterStopMode) refers to hk32f030m_exti.o(i.EXTI_ClearFlag) for EXTI_ClearFlag
hk32f030m_pwr.o(i.Sysclk_SwitchToLSI) refers to hk32f030m_rcc.o(i.RCC_LSICmd) for RCC_LSICmd
hk32f030m_pwr.o(i.Sysclk_SwitchToLSI) refers to hk32f030m_rcc.o(i.RCC_GetFlagStatus) for RCC_GetFlagStatus
hk32f030m_pwr.o(i.Sysclk_SwitchToLSI) refers to hk32f030m_rcc.o(i.RCC_HSICmd) for RCC_HSICmd
hk32f030m_rcc.o(i.RCC_EXTCmd) refers to hk32f030m_rcc.o(i.RCC_AHBPeriphClockCmd) for RCC_AHBPeriphClockCmd
hk32f030m_rcc.o(i.RCC_EXTCmd) refers to hk32f030m_gpio.o(i.GPIO_Init) for GPIO_Init
hk32f030m_rcc.o(i.RCC_GetClocksFreq) refers to uidiv.o(.text) for __aeabi_uidivmod
hk32f030m_rcc.o(i.RCC_GetClocksFreq) refers to hk32f030m_rcc.o(.constdata) for .constdata
hk32f030m_rcc.o(i.RCC_WaitForStartUp) refers to hk32f030m_rcc.o(i.RCC_GetFlagStatus) for RCC_GetFlagStatus
hk32f030m_spi.o(i.I2S_Init) refers to hk32f030m_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq
hk32f030m_spi.o(i.I2S_Init) refers to uidiv.o(.text) for __aeabi_uidivmod
hk32f030m_spi.o(i.SPI_I2S_DeInit) refers to hk32f030m_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
hk32f030m_syscfg.o(i.SYSCFG_DeInit) refers to hk32f030m_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
hk32f030m_tim.o(i.TIM_DeInit) refers to hk32f030m_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
hk32f030m_tim.o(i.TIM_DeInit) refers to hk32f030m_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd
hk32f030m_tim.o(i.TIM_ETRClockMode1Config) refers to hk32f030m_tim.o(i.TIM_ETRConfig) for TIM_ETRConfig
hk32f030m_tim.o(i.TIM_ETRClockMode2Config) refers to hk32f030m_tim.o(i.TIM_ETRConfig) for TIM_ETRConfig
hk32f030m_tim.o(i.TIM_ICInit) refers to hk32f030m_tim.o(i.TIM_SetIC4Prescaler) for TIM_SetIC4Prescaler
hk32f030m_tim.o(i.TIM_ICInit) refers to hk32f030m_tim.o(i.TI1_Config) for TI1_Config
hk32f030m_tim.o(i.TIM_ICInit) refers to hk32f030m_tim.o(i.TIM_SetIC1Prescaler) for TIM_SetIC1Prescaler
hk32f030m_tim.o(i.TIM_ICInit) refers to hk32f030m_tim.o(i.TI2_Config) for TI2_Config
hk32f030m_tim.o(i.TIM_ICInit) refers to hk32f030m_tim.o(i.TIM_SetIC2Prescaler) for TIM_SetIC2Prescaler
hk32f030m_tim.o(i.TIM_ICInit) refers to hk32f030m_tim.o(i.TIM_SetIC3Prescaler) for TIM_SetIC3Prescaler
hk32f030m_tim.o(i.TIM_ITRxExternalClockConfig) refers to hk32f030m_tim.o(i.TIM_SelectInputTrigger) for TIM_SelectInputTrigger
hk32f030m_tim.o(i.TIM_PWMIConfig) refers to hk32f030m_tim.o(i.TI2_Config) for TI2_Config
hk32f030m_tim.o(i.TIM_PWMIConfig) refers to hk32f030m_tim.o(i.TIM_SetIC2Prescaler) for TIM_SetIC2Prescaler
hk32f030m_tim.o(i.TIM_PWMIConfig) refers to hk32f030m_tim.o(i.TI1_Config) for TI1_Config
hk32f030m_tim.o(i.TIM_PWMIConfig) refers to hk32f030m_tim.o(i.TIM_SetIC1Prescaler) for TIM_SetIC1Prescaler
hk32f030m_tim.o(i.TIM_TIxExternalClockConfig) refers to hk32f030m_tim.o(i.TI1_Config) for TI1_Config
hk32f030m_tim.o(i.TIM_TIxExternalClockConfig) refers to hk32f030m_tim.o(i.TIM_SelectInputTrigger) for TIM_SelectInputTrigger
hk32f030m_tim.o(i.TIM_TIxExternalClockConfig) refers to hk32f030m_tim.o(i.TI2_Config) for TI2_Config
hk32f030m_usart.o(i.USART_DeInit) refers to hk32f030m_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
hk32f030m_usart.o(i.USART_Init) refers to hk32f030m_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq
hk32f030m_usart.o(i.USART_Init) refers to uidiv.o(.text) for __aeabi_uidivmod
hk32f030m_wwdg.o(i.WWDG_DeInit) refers to hk32f030m_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd
system_hk32f030m.o(i.SystemCoreClockUpdate) refers to uidiv.o(.text) for __aeabi_uidivmod
system_hk32f030m.o(i.SystemCoreClockUpdate) refers to system_hk32f030m.o(.data) for .data
system_hk32f030m.o(i.SystemCoreClockUpdate) refers to hk32f030m_rcc.o(.constdata) for AHBPrescTable
system_hk32f030m.o(i.SystemInit) refers to system_hk32f030m.o(i.SetSysClockToHSI_32M) for SetSysClockToHSI_32M
keil_startup_hk32f030m.o(RESET) refers to keil_startup_hk32f030m.o(STACK) for __initial_sp
keil_startup_hk32f030m.o(RESET) refers to keil_startup_hk32f030m.o(.text) for Reset_Handler
keil_startup_hk32f030m.o(RESET) refers to hk32f030m_it.o(i.NMI_Handler) for NMI_Handler
keil_startup_hk32f030m.o(RESET) refers to hk32f030m_it.o(i.HardFault_Handler) for HardFault_Handler
keil_startup_hk32f030m.o(RESET) refers to hk32f030m_it.o(i.SVC_Handler) for SVC_Handler
keil_startup_hk32f030m.o(RESET) refers to hk32f030m_it.o(i.PendSV_Handler) for PendSV_Handler
keil_startup_hk32f030m.o(RESET) refers to hk32f030m_it.o(i.SysTick_Handler) for SysTick_Handler
keil_startup_hk32f030m.o(.text) refers to system_hk32f030m.o(i.SystemInit) for SystemInit
keil_startup_hk32f030m.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000D) for __rt_final_cpp
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$0000000F) for __rt_final_exit
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk
entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000
entry2.o(.ARM.Collect$$$$00002712) refers to keil_startup_hk32f030m.o(STACK) for __initial_sp
entry2.o(__vectab_stack_and_reset_area) refers to keil_startup_hk32f030m.o(STACK) for __initial_sp
entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main
entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload
entry9a.o(.ARM.Collect$$$$0000000B) refers to main.o(i.main) for main
entry9b.o(.ARM.Collect$$$$0000000C) refers to main.o(i.main) for main
init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload
==============================================================================
Removing Unused input sections from the image.
Removing hk32f030m_it.o(.rev16_text), (4 bytes).
Removing hk32f030m_it.o(.revsh_text), (4 bytes).
Removing main.o(.rev16_text), (4 bytes).
Removing main.o(.revsh_text), (4 bytes).
Removing main.o(i.Delay), (16 bytes).
Removing bsp_led.o(.rev16_text), (4 bytes).
Removing bsp_led.o(.revsh_text), (4 bytes).
Removing hk32f030m_adc.o(.rev16_text), (4 bytes).
Removing hk32f030m_adc.o(.revsh_text), (4 bytes).
Removing hk32f030m_adc.o(i.ADC_AWDWakeup_Cmd), (26 bytes).
Removing hk32f030m_adc.o(i.ADC_AnalogWatchdogCmd), (20 bytes).
Removing hk32f030m_adc.o(i.ADC_AnalogWatchdogSingleChannelCmd), (20 bytes).
Removing hk32f030m_adc.o(i.ADC_AnalogWatchdogSingleChannelConfig), (14 bytes).
Removing hk32f030m_adc.o(i.ADC_AnalogWatchdogThresholdsConfig), (8 bytes).
Removing hk32f030m_adc.o(i.ADC_AutoPowerOffCmd), (20 bytes).
Removing hk32f030m_adc.o(i.ADC_ChannelConfig), (6 bytes).
Removing hk32f030m_adc.o(i.ADC_ClearFlag), (4 bytes).
Removing hk32f030m_adc.o(i.ADC_ClearITPendingBit), (4 bytes).
Removing hk32f030m_adc.o(i.ADC_ClockModeConfig), (4 bytes).
Removing hk32f030m_adc.o(i.ADC_Cmd), (18 bytes).
Removing hk32f030m_adc.o(i.ADC_ContinuousModeCmd), (20 bytes).
Removing hk32f030m_adc.o(i.ADC_DeInit), (32 bytes).
Removing hk32f030m_adc.o(i.ADC_Diff_Func), (24 bytes).
Removing hk32f030m_adc.o(i.ADC_DiscModeCmd), (20 bytes).
Removing hk32f030m_adc.o(i.ADC_GetCalibrationFactor), (46 bytes).
Removing hk32f030m_adc.o(i.ADC_GetConversionValue), (6 bytes).
Removing hk32f030m_adc.o(i.ADC_GetFlagStatus), (28 bytes).
Removing hk32f030m_adc.o(i.ADC_GetITStatus), (22 bytes).
Removing hk32f030m_adc.o(i.ADC_ITConfig), (16 bytes).
Removing hk32f030m_adc.o(i.ADC_Init), (40 bytes).
Removing hk32f030m_adc.o(i.ADC_InterDelay_Func), (26 bytes).
Removing hk32f030m_adc.o(i.ADC_JitterCmd), (16 bytes).
Removing hk32f030m_adc.o(i.ADC_OverrunModeCmd), (20 bytes).
Removing hk32f030m_adc.o(i.ADC_StartOfConversion), (10 bytes).
Removing hk32f030m_adc.o(i.ADC_StopOfConversion), (10 bytes).
Removing hk32f030m_adc.o(i.ADC_StructInit), (14 bytes).
Removing hk32f030m_adc.o(i.ADC_VrefintCmd), (26 bytes).
Removing hk32f030m_adc.o(i.ADC_WaitModeCmd), (20 bytes).
Removing hk32f030m_awu.o(.rev16_text), (4 bytes).
Removing hk32f030m_awu.o(.revsh_text), (4 bytes).
Removing hk32f030m_awu.o(i.AWU_CLKConfig), (24 bytes).
Removing hk32f030m_awu.o(i.AWU_DeInit), (16 bytes).
Removing hk32f030m_awu.o(i.AWU_GetFlagStatus), (16 bytes).
Removing hk32f030m_awu.o(i.AWU_TimerCounterAndStart), (60 bytes).
Removing hk32f030m_beep.o(.rev16_text), (4 bytes).
Removing hk32f030m_beep.o(.revsh_text), (4 bytes).
Removing hk32f030m_beep.o(i.BEEP_ClockSelect), (28 bytes).
Removing hk32f030m_beep.o(i.BEEP_Cmd), (40 bytes).
Removing hk32f030m_beep.o(i.BEEP_DeInit), (28 bytes).
Removing hk32f030m_beep.o(i.BEEP_Init), (84 bytes).
Removing hk32f030m_beep.o(i.BEEP_ReadBeepStatus), (20 bytes).
Removing hk32f030m_beep.o(i.BEEP_SetPrescaler), (20 bytes).
Removing hk32f030m_beep.o(i.BEEP_SetTRGOPrescaler), (20 bytes).
Removing hk32f030m_beep.o(i.BEEP_TRGOCmd), (40 bytes).
Removing hk32f030m_crc.o(.rev16_text), (4 bytes).
Removing hk32f030m_crc.o(.revsh_text), (4 bytes).
Removing hk32f030m_crc.o(i.CRC_CalcBlockCRC), (28 bytes).
Removing hk32f030m_crc.o(i.CRC_CalcCRC), (12 bytes).
Removing hk32f030m_crc.o(i.CRC_DeInit), (24 bytes).
Removing hk32f030m_crc.o(i.CRC_GetCRC), (12 bytes).
Removing hk32f030m_crc.o(i.CRC_GetIDRegister), (12 bytes).
Removing hk32f030m_crc.o(i.CRC_ResetDR), (16 bytes).
Removing hk32f030m_crc.o(i.CRC_ReverseInputDataSelect), (20 bytes).
Removing hk32f030m_crc.o(i.CRC_ReverseOutputDataCmd), (24 bytes).
Removing hk32f030m_crc.o(i.CRC_SetIDRegister), (12 bytes).
Removing hk32f030m_crc.o(i.CRC_SetInitRegister), (12 bytes).
Removing hk32f030m_exti.o(.rev16_text), (4 bytes).
Removing hk32f030m_exti.o(.revsh_text), (4 bytes).
Removing hk32f030m_exti.o(i.EXTI_ClearFlag), (12 bytes).
Removing hk32f030m_exti.o(i.EXTI_ClearITPendingBit), (12 bytes).
Removing hk32f030m_exti.o(i.EXTI_DeInit), (24 bytes).
Removing hk32f030m_exti.o(i.EXTI_GenerateSWInterrupt), (16 bytes).
Removing hk32f030m_exti.o(i.EXTI_GetFlagStatus), (20 bytes).
Removing hk32f030m_exti.o(i.EXTI_GetITStatus), (28 bytes).
Removing hk32f030m_exti.o(i.EXTI_Init), (108 bytes).
Removing hk32f030m_exti.o(i.EXTI_StructInit), (14 bytes).
Removing hk32f030m_flash.o(.rev16_text), (4 bytes).
Removing hk32f030m_flash.o(.revsh_text), (4 bytes).
Removing hk32f030m_flash.o(i.EEPROM_EraseByte), (60 bytes).
Removing hk32f030m_flash.o(i.EEPROM_ProgramByte), (52 bytes).
Removing hk32f030m_flash.o(i.FLASH_ClearFlag), (12 bytes).
Removing hk32f030m_flash.o(i.FLASH_EraseAllPages), (52 bytes).
Removing hk32f030m_flash.o(i.FLASH_ErasePage), (56 bytes).
Removing hk32f030m_flash.o(i.FLASH_GetFlagStatus), (20 bytes).
Removing hk32f030m_flash.o(i.FLASH_GetStatus), (28 bytes).
Removing hk32f030m_flash.o(i.FLASH_ITConfig), (24 bytes).
Removing hk32f030m_flash.o(i.FLASH_Lock), (16 bytes).
Removing hk32f030m_flash.o(i.FLASH_OB_DBGCLKConfig), (120 bytes).
Removing hk32f030m_flash.o(i.FLASH_OB_EraseByte), (56 bytes).
Removing hk32f030m_flash.o(i.FLASH_OB_GetRDP), (20 bytes).
Removing hk32f030m_flash.o(i.FLASH_OB_GetUser), (16 bytes).
Removing hk32f030m_flash.o(i.FLASH_OB_GetWRP), (12 bytes).
Removing hk32f030m_flash.o(i.FLASH_OB_IWDG_RLRConfig), (144 bytes).
Removing hk32f030m_flash.o(i.FLASH_OB_LSILPConfig), (120 bytes).
Removing hk32f030m_flash.o(i.FLASH_OB_Lock), (16 bytes).
Removing hk32f030m_flash.o(i.FLASH_OB_ProgramData), (56 bytes).
Removing hk32f030m_flash.o(i.FLASH_OB_RDPConfig), (124 bytes).
Removing hk32f030m_flash.o(i.FLASH_OB_Unlock), (32 bytes).
Removing hk32f030m_flash.o(i.FLASH_OB_UserConfig), (128 bytes).
Removing hk32f030m_flash.o(i.FLASH_OB_WRPConfig), (196 bytes).
Removing hk32f030m_flash.o(i.FLASH_OB_WriteUser), (60 bytes).
Removing hk32f030m_flash.o(i.FLASH_ProgramByte), (52 bytes).
Removing hk32f030m_flash.o(i.FLASH_ProgramHalfWord), (52 bytes).
Removing hk32f030m_flash.o(i.FLASH_SetLatency), (20 bytes).
Removing hk32f030m_flash.o(i.FLASH_Unlock), (32 bytes).
Removing hk32f030m_flash.o(i.FLASH_WaitForLastOperation), (34 bytes).
Removing hk32f030m_flash.o(i.Sys_GetDevice64BitUID), (16 bytes).
Removing hk32f030m_gpio.o(.rev16_text), (4 bytes).
Removing hk32f030m_gpio.o(.revsh_text), (4 bytes).
Removing hk32f030m_gpio.o(i.GPIO_DeInit), (80 bytes).
Removing hk32f030m_gpio.o(i.GPIO_IOMUX_ChangePin), (44 bytes).
Removing hk32f030m_gpio.o(i.GPIO_IOMUX_PinAFConfig), (108 bytes).
Removing hk32f030m_gpio.o(i.GPIO_IOMUX_SetTIM2CN1_Source), (12 bytes).
Removing hk32f030m_gpio.o(i.GPIO_PinAFConfig), (32 bytes).
Removing hk32f030m_gpio.o(i.GPIO_PinLockConfig), (26 bytes).
Removing hk32f030m_gpio.o(i.GPIO_ReadInputData), (6 bytes).
Removing hk32f030m_gpio.o(i.GPIO_ReadInputDataBit), (14 bytes).
Removing hk32f030m_gpio.o(i.GPIO_ReadOutputData), (6 bytes).
Removing hk32f030m_gpio.o(i.GPIO_ReadOutputDataBit), (14 bytes).
Removing hk32f030m_gpio.o(i.GPIO_ResetBits), (4 bytes).
Removing hk32f030m_gpio.o(i.GPIO_StructInit), (24 bytes).
Removing hk32f030m_gpio.o(i.GPIO_Toggle), (8 bytes).
Removing hk32f030m_gpio.o(i.GPIO_Write), (4 bytes).
Removing hk32f030m_gpio.o(i.GPIO_WriteBit), (12 bytes).
Removing hk32f030m_i2c.o(.rev16_text), (4 bytes).
Removing hk32f030m_i2c.o(.revsh_text), (4 bytes).
Removing hk32f030m_i2c.o(i.I2C_10BitAddressHeaderCmd), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_10BitAddressingModeCmd), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_AcknowledgeConfig), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_AutoEndCmd), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_CalculatePEC), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_ClearFlag), (4 bytes).
Removing hk32f030m_i2c.o(i.I2C_ClearITPendingBit), (4 bytes).
Removing hk32f030m_i2c.o(i.I2C_ClockTimeoutCmd), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_Cmd), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_DeInit), (32 bytes).
Removing hk32f030m_i2c.o(i.I2C_DualAddressCmd), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_ExtendedClockTimeoutCmd), (22 bytes).
Removing hk32f030m_i2c.o(i.I2C_GeneralCallCmd), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_GenerateSTART), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_GenerateSTOP), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_GetAddressMatched), (10 bytes).
Removing hk32f030m_i2c.o(i.I2C_GetFlagStatus), (14 bytes).
Removing hk32f030m_i2c.o(i.I2C_GetITStatus), (48 bytes).
Removing hk32f030m_i2c.o(i.I2C_GetPEC), (6 bytes).
Removing hk32f030m_i2c.o(i.I2C_GetTransferDirection), (18 bytes).
Removing hk32f030m_i2c.o(i.I2C_ITConfig), (16 bytes).
Removing hk32f030m_i2c.o(i.I2C_IdleClockTimeoutCmd), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_Init), (100 bytes).
Removing hk32f030m_i2c.o(i.I2C_MasterRequestConfig), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_NumberOfBytesConfig), (16 bytes).
Removing hk32f030m_i2c.o(i.I2C_OwnAddress2Config), (28 bytes).
Removing hk32f030m_i2c.o(i.I2C_PECRequestCmd), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_ReadRegister), (10 bytes).
Removing hk32f030m_i2c.o(i.I2C_ReceiveData), (6 bytes).
Removing hk32f030m_i2c.o(i.I2C_ReloadCmd), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_SMBusAlertCmd), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_SendData), (4 bytes).
Removing hk32f030m_i2c.o(i.I2C_SlaveAddressConfig), (16 bytes).
Removing hk32f030m_i2c.o(i.I2C_SlaveByteControlCmd), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_SoftwareResetCmd), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_StopModeCmd), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_StretchClockCmd), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_StructInit), (22 bytes).
Removing hk32f030m_i2c.o(i.I2C_TimeoutAConfig), (16 bytes).
Removing hk32f030m_i2c.o(i.I2C_TimeoutBConfig), (20 bytes).
Removing hk32f030m_i2c.o(i.I2C_TransferHandling), (32 bytes).
Removing hk32f030m_iwdg.o(.rev16_text), (4 bytes).
Removing hk32f030m_iwdg.o(.revsh_text), (4 bytes).
Removing hk32f030m_iwdg.o(i.IWDG_Enable), (16 bytes).
Removing hk32f030m_iwdg.o(i.IWDG_GetFlagStatus), (20 bytes).
Removing hk32f030m_iwdg.o(i.IWDG_ReloadCounter), (16 bytes).
Removing hk32f030m_iwdg.o(i.IWDG_SetPrescaler), (12 bytes).
Removing hk32f030m_iwdg.o(i.IWDG_SetReload), (12 bytes).
Removing hk32f030m_iwdg.o(i.IWDG_SetWindowValue), (12 bytes).
Removing hk32f030m_iwdg.o(i.IWDG_WriteAccessCmd), (12 bytes).
Removing hk32f030m_misc.o(.rev16_text), (4 bytes).
Removing hk32f030m_misc.o(.revsh_text), (4 bytes).
Removing hk32f030m_misc.o(i.NVIC_Init), (80 bytes).
Removing hk32f030m_misc.o(i.NVIC_SystemLPConfig), (24 bytes).
Removing hk32f030m_misc.o(i.SysTick_CLKSourceConfig), (24 bytes).
Removing hk32f030m_pwr.o(.rev16_text), (4 bytes).
Removing hk32f030m_pwr.o(.revsh_text), (4 bytes).
Removing hk32f030m_pwr.o(i.PWR_DeInit), (22 bytes).
Removing hk32f030m_pwr.o(i.PWR_EnterDeepSleepMode), (16 bytes).
Removing hk32f030m_pwr.o(i.PWR_EnterSleepMode), (32 bytes).
Removing hk32f030m_pwr.o(i.PWR_EnterStopMode), (88 bytes).
Removing hk32f030m_pwr.o(i.PWR_SetLDO_RefVolToADC), (24 bytes).
Removing hk32f030m_pwr.o(i.Sysclk_SwitchToLSI), (104 bytes).
Removing hk32f030m_rcc.o(.rev16_text), (4 bytes).
Removing hk32f030m_rcc.o(.revsh_text), (4 bytes).
Removing hk32f030m_rcc.o(i.RCC_ADCCLKConfig), (60 bytes).
Removing hk32f030m_rcc.o(i.RCC_AHBPeriphResetCmd), (24 bytes).
Removing hk32f030m_rcc.o(i.RCC_APB1PeriphClockCmd), (24 bytes).
Removing hk32f030m_rcc.o(i.RCC_APB1PeriphResetCmd), (24 bytes).
Removing hk32f030m_rcc.o(i.RCC_APB2PeriphClockCmd), (24 bytes).
Removing hk32f030m_rcc.o(i.RCC_APB2PeriphResetCmd), (24 bytes).
Removing hk32f030m_rcc.o(i.RCC_AdjustHSICalibrationValue), (20 bytes).
Removing hk32f030m_rcc.o(i.RCC_ClearFlag), (20 bytes).
Removing hk32f030m_rcc.o(i.RCC_ClearITPendingBit), (12 bytes).
Removing hk32f030m_rcc.o(i.RCC_ClockSecuritySystemCmd), (28 bytes).
Removing hk32f030m_rcc.o(i.RCC_DeInit), (40 bytes).
Removing hk32f030m_rcc.o(i.RCC_EXTCmd), (80 bytes).
Removing hk32f030m_rcc.o(i.RCC_GetClocksFreq), (200 bytes).
Removing hk32f030m_rcc.o(i.RCC_GetFlagStatus), (48 bytes).
Removing hk32f030m_rcc.o(i.RCC_GetITStatus), (20 bytes).
Removing hk32f030m_rcc.o(i.RCC_GetSYSCLKSource), (16 bytes).
Removing hk32f030m_rcc.o(i.RCC_HCLKConfig), (20 bytes).
Removing hk32f030m_rcc.o(i.RCC_HSICmd), (28 bytes).
Removing hk32f030m_rcc.o(i.RCC_I2CCLKConfig), (24 bytes).
Removing hk32f030m_rcc.o(i.RCC_ITConfig), (24 bytes).
Removing hk32f030m_rcc.o(i.RCC_LSICmd), (28 bytes).
Removing hk32f030m_rcc.o(i.RCC_MCOConfig), (28 bytes).
Removing hk32f030m_rcc.o(i.RCC_PCLKConfig), (20 bytes).
Removing hk32f030m_rcc.o(i.RCC_SYSCLKConfig), (20 bytes).
Removing hk32f030m_rcc.o(i.RCC_USARTCLKConfig), (24 bytes).
Removing hk32f030m_rcc.o(i.RCC_WaitForStartUp), (48 bytes).
Removing hk32f030m_rcc.o(.constdata), (40 bytes).
Removing hk32f030m_spi.o(.rev16_text), (4 bytes).
Removing hk32f030m_spi.o(.revsh_text), (4 bytes).
Removing hk32f030m_spi.o(i.I2S_Cmd), (28 bytes).
Removing hk32f030m_spi.o(i.I2S_Init), (160 bytes).
Removing hk32f030m_spi.o(i.I2S_StructInit), (18 bytes).
Removing hk32f030m_spi.o(i.SPI_BiDirectionalLineConfig), (28 bytes).
Removing hk32f030m_spi.o(i.SPI_CRCLengthConfig), (20 bytes).
Removing hk32f030m_spi.o(i.SPI_CalculateCRC), (28 bytes).
Removing hk32f030m_spi.o(i.SPI_Cmd), (24 bytes).
Removing hk32f030m_spi.o(i.SPI_DataSizeConfig), (20 bytes).
Removing hk32f030m_spi.o(i.SPI_GetCRC), (14 bytes).
Removing hk32f030m_spi.o(i.SPI_GetCRCPolynomial), (6 bytes).
Removing hk32f030m_spi.o(i.SPI_GetReceptionFIFOStatus), (10 bytes).
Removing hk32f030m_spi.o(i.SPI_GetTransmissionFIFOStatus), (10 bytes).
Removing hk32f030m_spi.o(i.SPI_I2S_ClearFlag), (8 bytes).
Removing hk32f030m_spi.o(i.SPI_I2S_DeInit), (32 bytes).
Removing hk32f030m_spi.o(i.SPI_I2S_GetFlagStatus), (14 bytes).
Removing hk32f030m_spi.o(i.SPI_I2S_GetITStatus), (42 bytes).
Removing hk32f030m_spi.o(i.SPI_I2S_ITConfig), (28 bytes).
Removing hk32f030m_spi.o(i.SPI_I2S_ReceiveData16), (6 bytes).
Removing hk32f030m_spi.o(i.SPI_I2S_SendData16), (4 bytes).
Removing hk32f030m_spi.o(i.SPI_Init), (88 bytes).
Removing hk32f030m_spi.o(i.SPI_NSSInternalSoftwareConfig), (28 bytes).
Removing hk32f030m_spi.o(i.SPI_NSSPulseModeCmd), (24 bytes).
Removing hk32f030m_spi.o(i.SPI_ReceiveData8), (4 bytes).
Removing hk32f030m_spi.o(i.SPI_RxFIFOThresholdConfig), (20 bytes).
Removing hk32f030m_spi.o(i.SPI_SSOutputCmd), (24 bytes).
Removing hk32f030m_spi.o(i.SPI_SendData8), (4 bytes).
Removing hk32f030m_spi.o(i.SPI_StructInit), (28 bytes).
Removing hk32f030m_spi.o(i.SPI_TIModeCmd), (24 bytes).
Removing hk32f030m_spi.o(i.SPI_TransmitCRC), (12 bytes).
Removing hk32f030m_syscfg.o(.rev16_text), (4 bytes).
Removing hk32f030m_syscfg.o(.revsh_text), (4 bytes).
Removing hk32f030m_syscfg.o(i.SYSCFG_DeInit), (20 bytes).
Removing hk32f030m_syscfg.o(i.SYSCFG_EXTILineConfig), (40 bytes).
Removing hk32f030m_syscfg.o(i.SYSCFG_Lockup_Tim1BreakConfig), (24 bytes).
Removing hk32f030m_syscfg.o(i.SYSCFG_MemoryRemapConfig), (28 bytes).
Removing hk32f030m_tim.o(.rev16_text), (4 bytes).
Removing hk32f030m_tim.o(.revsh_text), (4 bytes).
Removing hk32f030m_tim.o(i.TI1_Config), (52 bytes).
Removing hk32f030m_tim.o(i.TI2_Config), (64 bytes).
Removing hk32f030m_tim.o(i.TIM_ARRPreloadConfig), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_BDTRConfig), (32 bytes).
Removing hk32f030m_tim.o(i.TIM_BDTRStructInit), (18 bytes).
Removing hk32f030m_tim.o(i.TIM_CCPreloadControl), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_CCxCmd), (28 bytes).
Removing hk32f030m_tim.o(i.TIM_CCxNCmd), (28 bytes).
Removing hk32f030m_tim.o(i.TIM_ClearFlag), (8 bytes).
Removing hk32f030m_tim.o(i.TIM_ClearITPendingBit), (8 bytes).
Removing hk32f030m_tim.o(i.TIM_ClearOC1Ref), (14 bytes).
Removing hk32f030m_tim.o(i.TIM_ClearOC2Ref), (16 bytes).
Removing hk32f030m_tim.o(i.TIM_ClearOC3Ref), (14 bytes).
Removing hk32f030m_tim.o(i.TIM_ClearOC4Ref), (16 bytes).
Removing hk32f030m_tim.o(i.TIM_Cmd), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_CounterModeConfig), (14 bytes).
Removing hk32f030m_tim.o(i.TIM_CtrlPWMOutputs), (22 bytes).
Removing hk32f030m_tim.o(i.TIM_DeInit), (84 bytes).
Removing hk32f030m_tim.o(i.TIM_ETRClockMode1Config), (30 bytes).
Removing hk32f030m_tim.o(i.TIM_ETRClockMode2Config), (20 bytes).
Removing hk32f030m_tim.o(i.TIM_ETRConfig), (20 bytes).
Removing hk32f030m_tim.o(i.TIM_EncoderInterfaceConfig), (56 bytes).
Removing hk32f030m_tim.o(i.TIM_ForcedOC1Config), (14 bytes).
Removing hk32f030m_tim.o(i.TIM_ForcedOC2Config), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_ForcedOC3Config), (14 bytes).
Removing hk32f030m_tim.o(i.TIM_ForcedOC4Config), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_GenerateEvent), (4 bytes).
Removing hk32f030m_tim.o(i.TIM_GetCapture1), (4 bytes).
Removing hk32f030m_tim.o(i.TIM_GetCapture2), (4 bytes).
Removing hk32f030m_tim.o(i.TIM_GetCapture3), (4 bytes).
Removing hk32f030m_tim.o(i.TIM_GetCapture4), (4 bytes).
Removing hk32f030m_tim.o(i.TIM_GetCounter), (4 bytes).
Removing hk32f030m_tim.o(i.TIM_GetFlagStatus), (14 bytes).
Removing hk32f030m_tim.o(i.TIM_GetITStatus), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_GetPrescaler), (6 bytes).
Removing hk32f030m_tim.o(i.TIM_ICInit), (196 bytes).
Removing hk32f030m_tim.o(i.TIM_ICStructInit), (16 bytes).
Removing hk32f030m_tim.o(i.TIM_ITConfig), (20 bytes).
Removing hk32f030m_tim.o(i.TIM_ITRxExternalClockConfig), (18 bytes).
Removing hk32f030m_tim.o(i.TIM_InternalClockConfig), (16 bytes).
Removing hk32f030m_tim.o(i.TIM_OC1FastConfig), (14 bytes).
Removing hk32f030m_tim.o(i.TIM_OC1Init), (104 bytes).
Removing hk32f030m_tim.o(i.TIM_OC1NPolarityConfig), (14 bytes).
Removing hk32f030m_tim.o(i.TIM_OC1PolarityConfig), (14 bytes).
Removing hk32f030m_tim.o(i.TIM_OC1PreloadConfig), (14 bytes).
Removing hk32f030m_tim.o(i.TIM_OC2FastConfig), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_OC2Init), (140 bytes).
Removing hk32f030m_tim.o(i.TIM_OC2NPolarityConfig), (18 bytes).
Removing hk32f030m_tim.o(i.TIM_OC2PolarityConfig), (18 bytes).
Removing hk32f030m_tim.o(i.TIM_OC2PreloadConfig), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_OC3FastConfig), (14 bytes).
Removing hk32f030m_tim.o(i.TIM_OC3Init), (140 bytes).
Removing hk32f030m_tim.o(i.TIM_OC3NPolarityConfig), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_OC3PolarityConfig), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_OC3PreloadConfig), (14 bytes).
Removing hk32f030m_tim.o(i.TIM_OC4FastConfig), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_OC4Init), (104 bytes).
Removing hk32f030m_tim.o(i.TIM_OC4PolarityConfig), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_OC4PreloadConfig), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_OCStructInit), (20 bytes).
Removing hk32f030m_tim.o(i.TIM_PWMIConfig), (104 bytes).
Removing hk32f030m_tim.o(i.TIM_PrescalerConfig), (6 bytes).
Removing hk32f030m_tim.o(i.TIM_SelectCOM), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_SelectHallSensor), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_SelectInputTrigger), (14 bytes).
Removing hk32f030m_tim.o(i.TIM_SelectMasterSlaveMode), (20 bytes).
Removing hk32f030m_tim.o(i.TIM_SelectOCREFClear), (20 bytes).
Removing hk32f030m_tim.o(i.TIM_SelectOCxM), (74 bytes).
Removing hk32f030m_tim.o(i.TIM_SelectOnePulseMode), (20 bytes).
Removing hk32f030m_tim.o(i.TIM_SelectOutputTrigger), (20 bytes).
Removing hk32f030m_tim.o(i.TIM_SelectSlaveMode), (20 bytes).
Removing hk32f030m_tim.o(i.TIM_SetAutoreload), (4 bytes).
Removing hk32f030m_tim.o(i.TIM_SetClockDivision), (20 bytes).
Removing hk32f030m_tim.o(i.TIM_SetCompare1), (4 bytes).
Removing hk32f030m_tim.o(i.TIM_SetCompare2), (4 bytes).
Removing hk32f030m_tim.o(i.TIM_SetCompare3), (4 bytes).
Removing hk32f030m_tim.o(i.TIM_SetCompare4), (4 bytes).
Removing hk32f030m_tim.o(i.TIM_SetCounter), (4 bytes).
Removing hk32f030m_tim.o(i.TIM_SetIC1Prescaler), (20 bytes).
Removing hk32f030m_tim.o(i.TIM_SetIC2Prescaler), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_SetIC3Prescaler), (20 bytes).
Removing hk32f030m_tim.o(i.TIM_SetIC4Prescaler), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_TIxExternalClockConfig), (48 bytes).
Removing hk32f030m_tim.o(i.TIM_TimeBaseInit), (80 bytes).
Removing hk32f030m_tim.o(i.TIM_TimeBaseStructInit), (18 bytes).
Removing hk32f030m_tim.o(i.TIM_UpdateDisableConfig), (24 bytes).
Removing hk32f030m_tim.o(i.TIM_UpdateRequestConfig), (24 bytes).
Removing hk32f030m_usart.o(.rev16_text), (4 bytes).
Removing hk32f030m_usart.o(.revsh_text), (4 bytes).
Removing hk32f030m_usart.o(i.USART_AddressDetectionConfig), (16 bytes).
Removing hk32f030m_usart.o(i.USART_AutoBaudRateCmd), (20 bytes).
Removing hk32f030m_usart.o(i.USART_AutoBaudRateConfig), (18 bytes).
Removing hk32f030m_usart.o(i.USART_ClearFlag), (4 bytes).
Removing hk32f030m_usart.o(i.USART_ClearITPendingBit), (10 bytes).
Removing hk32f030m_usart.o(i.USART_ClockInit), (28 bytes).
Removing hk32f030m_usart.o(i.USART_ClockStructInit), (12 bytes).
Removing hk32f030m_usart.o(i.USART_Cmd), (20 bytes).
Removing hk32f030m_usart.o(i.USART_DECmd), (20 bytes).
Removing hk32f030m_usart.o(i.USART_DEPolarityConfig), (18 bytes).
Removing hk32f030m_usart.o(i.USART_DataInvCmd), (20 bytes).
Removing hk32f030m_usart.o(i.USART_DeInit), (32 bytes).
Removing hk32f030m_usart.o(i.USART_DirectionModeCmd), (16 bytes).
Removing hk32f030m_usart.o(i.USART_GetFlagStatus), (14 bytes).
Removing hk32f030m_usart.o(i.USART_GetITStatus), (56 bytes).
Removing hk32f030m_usart.o(i.USART_HalfDuplexCmd), (18 bytes).
Removing hk32f030m_usart.o(i.USART_ITConfig), (42 bytes).
Removing hk32f030m_usart.o(i.USART_Init), (144 bytes).
Removing hk32f030m_usart.o(i.USART_InvPinCmd), (16 bytes).
Removing hk32f030m_usart.o(i.USART_IrDACmd), (18 bytes).
Removing hk32f030m_usart.o(i.USART_IrDAConfig), (16 bytes).
Removing hk32f030m_usart.o(i.USART_LINBreakDetectLengthConfig), (16 bytes).
Removing hk32f030m_usart.o(i.USART_LINCmd), (20 bytes).
Removing hk32f030m_usart.o(i.USART_MSBFirstCmd), (20 bytes).
Removing hk32f030m_usart.o(i.USART_MuteModeCmd), (20 bytes).
Removing hk32f030m_usart.o(i.USART_MuteModeWakeUpConfig), (18 bytes).
Removing hk32f030m_usart.o(i.USART_OneBitMethodCmd), (20 bytes).
Removing hk32f030m_usart.o(i.USART_OverSampling8Cmd), (20 bytes).
Removing hk32f030m_usart.o(i.USART_OverrunDetectionConfig), (18 bytes).
Removing hk32f030m_usart.o(i.USART_ReceiveData), (8 bytes).
Removing hk32f030m_usart.o(i.USART_ReceiverTimeOutCmd), (20 bytes).
Removing hk32f030m_usart.o(i.USART_RequestCmd), (16 bytes).
Removing hk32f030m_usart.o(i.USART_STOPModeCmd), (18 bytes).
Removing hk32f030m_usart.o(i.USART_SWAPPinCmd), (20 bytes).
Removing hk32f030m_usart.o(i.USART_SendData), (8 bytes).
Removing hk32f030m_usart.o(i.USART_SetAddress), (18 bytes).
Removing hk32f030m_usart.o(i.USART_SetAutoRetryCount), (20 bytes).
Removing hk32f030m_usart.o(i.USART_SetBlockLength), (18 bytes).
Removing hk32f030m_usart.o(i.USART_SetDEAssertionTime), (20 bytes).
Removing hk32f030m_usart.o(i.USART_SetDEDeassertionTime), (20 bytes).
Removing hk32f030m_usart.o(i.USART_SetGuardTime), (16 bytes).
Removing hk32f030m_usart.o(i.USART_SetPrescaler), (18 bytes).
Removing hk32f030m_usart.o(i.USART_SetReceiverTimeOut), (16 bytes).
Removing hk32f030m_usart.o(i.USART_SmartCardCmd), (18 bytes).
Removing hk32f030m_usart.o(i.USART_SmartCardNACKCmd), (18 bytes).
Removing hk32f030m_usart.o(i.USART_StopModeWakeUpSourceConfig), (18 bytes).
Removing hk32f030m_usart.o(i.USART_StructInit), (22 bytes).
Removing hk32f030m_wwdg.o(.rev16_text), (4 bytes).
Removing hk32f030m_wwdg.o(.revsh_text), (4 bytes).
Removing hk32f030m_wwdg.o(i.WWDG_ClearFlag), (12 bytes).
Removing hk32f030m_wwdg.o(i.WWDG_DeInit), (22 bytes).
Removing hk32f030m_wwdg.o(i.WWDG_Enable), (16 bytes).
Removing hk32f030m_wwdg.o(i.WWDG_EnableIT), (16 bytes).
Removing hk32f030m_wwdg.o(i.WWDG_GetFlagStatus), (20 bytes).
Removing hk32f030m_wwdg.o(i.WWDG_SetCounter), (16 bytes).
Removing hk32f030m_wwdg.o(i.WWDG_SetPrescaler), (20 bytes).
Removing hk32f030m_wwdg.o(i.WWDG_SetWindowValue), (28 bytes).
Removing system_hk32f030m.o(.rev16_text), (4 bytes).
Removing system_hk32f030m.o(.revsh_text), (4 bytes).
Removing system_hk32f030m.o(i.SystemCoreClockUpdate), (72 bytes).
Removing system_hk32f030m.o(.data), (4 bytes).
Removing keil_startup_hk32f030m.o(HEAP), (512 bytes).
Removing hk32f030m_gpio.o(i.__ARM_common_switch8), (26 bytes).
409 unused section(s) (total 11020 bytes) removed from the image.
==============================================================================
Image Symbol Table
Local Symbols
Symbol Name Value Ov Type Size Object(Section)
../clib/microlib/division.c 0x00000000 Number 0 uidiv.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE
..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startup_hk32f030m.s 0x00000000 Number 0 keil_startup_hk32f030m.o ABSOLUTE
..\Source\Libraries\CMSIS\HK32F030M\Source\system_hk32f030m.c 0x00000000 Number 0 system_hk32f030m.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_adc.c 0x00000000 Number 0 hk32f030m_adc.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_awu.c 0x00000000 Number 0 hk32f030m_awu.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_beep.c 0x00000000 Number 0 hk32f030m_beep.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_crc.c 0x00000000 Number 0 hk32f030m_crc.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_exti.c 0x00000000 Number 0 hk32f030m_exti.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_flash.c 0x00000000 Number 0 hk32f030m_flash.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_gpio.c 0x00000000 Number 0 hk32f030m_gpio.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_i2c.c 0x00000000 Number 0 hk32f030m_i2c.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_iwdg.c 0x00000000 Number 0 hk32f030m_iwdg.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_misc.c 0x00000000 Number 0 hk32f030m_misc.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_pwr.c 0x00000000 Number 0 hk32f030m_pwr.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_rcc.c 0x00000000 Number 0 hk32f030m_rcc.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_spi.c 0x00000000 Number 0 hk32f030m_spi.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_syscfg.c 0x00000000 Number 0 hk32f030m_syscfg.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_tim.c 0x00000000 Number 0 hk32f030m_tim.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_usart.c 0x00000000 Number 0 hk32f030m_usart.o ABSOLUTE
..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_wwdg.c 0x00000000 Number 0 hk32f030m_wwdg.o ABSOLUTE
..\Source\User\hk32f030m_it.c 0x00000000 Number 0 hk32f030m_it.o ABSOLUTE
..\Source\User\led\bsp_led.c 0x00000000 Number 0 bsp_led.o ABSOLUTE
..\Source\User\main.c 0x00000000 Number 0 main.o ABSOLUTE
..\\Source\\Libraries\\CMSIS\\HK32F030M\\Source\\system_hk32f030m.c 0x00000000 Number 0 system_hk32f030m.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_adc.c 0x00000000 Number 0 hk32f030m_adc.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_awu.c 0x00000000 Number 0 hk32f030m_awu.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_beep.c 0x00000000 Number 0 hk32f030m_beep.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_crc.c 0x00000000 Number 0 hk32f030m_crc.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_exti.c 0x00000000 Number 0 hk32f030m_exti.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_flash.c 0x00000000 Number 0 hk32f030m_flash.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_gpio.c 0x00000000 Number 0 hk32f030m_gpio.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_i2c.c 0x00000000 Number 0 hk32f030m_i2c.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_iwdg.c 0x00000000 Number 0 hk32f030m_iwdg.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_misc.c 0x00000000 Number 0 hk32f030m_misc.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_pwr.c 0x00000000 Number 0 hk32f030m_pwr.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_rcc.c 0x00000000 Number 0 hk32f030m_rcc.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_spi.c 0x00000000 Number 0 hk32f030m_spi.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_syscfg.c 0x00000000 Number 0 hk32f030m_syscfg.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_tim.c 0x00000000 Number 0 hk32f030m_tim.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_usart.c 0x00000000 Number 0 hk32f030m_usart.o ABSOLUTE
..\\Source\\Libraries\\HK32F030M_Lib\\src\\hk32f030m_wwdg.c 0x00000000 Number 0 hk32f030m_wwdg.o ABSOLUTE
..\\Source\\User\\hk32f030m_it.c 0x00000000 Number 0 hk32f030m_it.o ABSOLUTE
..\\Source\\User\\led\\bsp_led.c 0x00000000 Number 0 bsp_led.o ABSOLUTE
..\\Source\\User\\main.c 0x00000000 Number 0 main.o ABSOLUTE
dc.s 0x00000000 Number 0 dc.o ABSOLUTE
handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE
init.s 0x00000000 Number 0 init.o ABSOLUTE
RESET 0x08000000 Section 192 keil_startup_hk32f030m.o(RESET)
.ARM.Collect$$$$00000000 0x080000c0 Section 0 entry.o(.ARM.Collect$$$$00000000)
.ARM.Collect$$$$00000001 0x080000c0 Section 4 entry2.o(.ARM.Collect$$$$00000001)
.ARM.Collect$$$$00000004 0x080000c4 Section 4 entry5.o(.ARM.Collect$$$$00000004)
.ARM.Collect$$$$00000008 0x080000c8 Section 0 entry7b.o(.ARM.Collect$$$$00000008)
.ARM.Collect$$$$0000000A 0x080000c8 Section 0 entry8b.o(.ARM.Collect$$$$0000000A)
.ARM.Collect$$$$0000000B 0x080000c8 Section 8 entry9a.o(.ARM.Collect$$$$0000000B)
.ARM.Collect$$$$0000000D 0x080000d0 Section 0 entry10a.o(.ARM.Collect$$$$0000000D)
.ARM.Collect$$$$0000000F 0x080000d0 Section 0 entry11a.o(.ARM.Collect$$$$0000000F)
.ARM.Collect$$$$00002712 0x080000d0 Section 4 entry2.o(.ARM.Collect$$$$00002712)
__lit__00000000 0x080000d0 Data 4 entry2.o(.ARM.Collect$$$$00002712)
.text 0x080000d4 Section 28 keil_startup_hk32f030m.o(.text)
.text 0x080000f0 Section 36 init.o(.text)
i.GPIO_Init 0x08000114 Section 0 hk32f030m_gpio.o(i.GPIO_Init)
i.GPIO_SetBits 0x08000198 Section 0 hk32f030m_gpio.o(i.GPIO_SetBits)
i.HardFault_Handler 0x0800019c Section 0 hk32f030m_it.o(i.HardFault_Handler)
i.LED_GPIO_Config 0x080001a0 Section 0 bsp_led.o(i.LED_GPIO_Config)
i.NMI_Handler 0x08000204 Section 0 hk32f030m_it.o(i.NMI_Handler)
i.PendSV_Handler 0x08000206 Section 0 hk32f030m_it.o(i.PendSV_Handler)
i.RCC_AHBPeriphClockCmd 0x08000208 Section 0 hk32f030m_rcc.o(i.RCC_AHBPeriphClockCmd)
i.SVC_Handler 0x08000220 Section 0 hk32f030m_it.o(i.SVC_Handler)
i.SetSysClockToHSI_32M 0x08000224 Section 0 system_hk32f030m.o(i.SetSysClockToHSI_32M)
SetSysClockToHSI_32M 0x08000225 Thumb Code 140 system_hk32f030m.o(i.SetSysClockToHSI_32M)
i.SysTick_Handler 0x080002bc Section 0 hk32f030m_it.o(i.SysTick_Handler)
i.SystemInit 0x080002c0 Section 0 system_hk32f030m.o(i.SystemInit)
i.__scatterload_copy 0x0800031c Section 14 handlers.o(i.__scatterload_copy)
i.__scatterload_null 0x0800032a Section 2 handlers.o(i.__scatterload_null)
i.__scatterload_zeroinit 0x0800032c Section 14 handlers.o(i.__scatterload_zeroinit)
i.main 0x0800033c Section 0 main.o(i.main)
STACK 0x20000000 Section 512 keil_startup_hk32f030m.o(STACK)
Global Symbols
Symbol Name Value Ov Type Size Object(Section)
BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE
__ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE
__cpp_initialize__aeabi_ - Undefined Weak Reference
__cxa_finalize - Undefined Weak Reference
__decompress - Undefined Weak Reference
_clock_init - Undefined Weak Reference
_microlib_exit - Undefined Weak Reference
__Vectors_Size 0x000000c0 Number 0 keil_startup_hk32f030m.o ABSOLUTE
__Vectors 0x08000000 Data 4 keil_startup_hk32f030m.o(RESET)
__Vectors_End 0x080000c0 Data 0 keil_startup_hk32f030m.o(RESET)
__main 0x080000c1 Thumb Code 0 entry.o(.ARM.Collect$$$$00000000)
_main_stk 0x080000c1 Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001)
_main_scatterload 0x080000c5 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004)
__main_after_scatterload 0x080000c9 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004)
_main_clock 0x080000c9 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008)
_main_cpp_init 0x080000c9 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A)
_main_init 0x080000c9 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B)
__rt_final_cpp 0x080000d1 Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000D)
__rt_final_exit 0x080000d1 Thumb Code 0 entry11a.o(.ARM.Collect$$$$0000000F)
Reset_Handler 0x080000d5 Thumb Code 8 keil_startup_hk32f030m.o(.text)
ADC1_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
EXTI0_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
EXTI11_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
EXTI1_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
EXTI2_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
EXTI3_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
EXTI4_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
EXTI5_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
EXTI6_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
EXTI7_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
FLASH_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
I2C1_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
RCC_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
SPI1_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
TIM1_BRK_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
TIM1_CC_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
TIM1_UP_TRG_COM_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
TIM2_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
TIM6_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
USART1_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
WWDG_IRQHandler 0x080000e7 Thumb Code 0 keil_startup_hk32f030m.o(.text)
__scatterload 0x080000f1 Thumb Code 28 init.o(.text)
__scatterload_rt2 0x080000f1 Thumb Code 0 init.o(.text)
GPIO_Init 0x08000115 Thumb Code 132 hk32f030m_gpio.o(i.GPIO_Init)
GPIO_SetBits 0x08000199 Thumb Code 4 hk32f030m_gpio.o(i.GPIO_SetBits)
HardFault_Handler 0x0800019d Thumb Code 2 hk32f030m_it.o(i.HardFault_Handler)
LED_GPIO_Config 0x080001a1 Thumb Code 92 bsp_led.o(i.LED_GPIO_Config)
NMI_Handler 0x08000205 Thumb Code 2 hk32f030m_it.o(i.NMI_Handler)
PendSV_Handler 0x08000207 Thumb Code 2 hk32f030m_it.o(i.PendSV_Handler)
RCC_AHBPeriphClockCmd 0x08000209 Thumb Code 18 hk32f030m_rcc.o(i.RCC_AHBPeriphClockCmd)
SVC_Handler 0x08000221 Thumb Code 2 hk32f030m_it.o(i.SVC_Handler)
SysTick_Handler 0x080002bd Thumb Code 2 hk32f030m_it.o(i.SysTick_Handler)
SystemInit 0x080002c1 Thumb Code 74 system_hk32f030m.o(i.SystemInit)
__scatterload_copy 0x0800031d Thumb Code 14 handlers.o(i.__scatterload_copy)
__scatterload_null 0x0800032b Thumb Code 2 handlers.o(i.__scatterload_null)
__scatterload_zeroinit 0x0800032d Thumb Code 14 handlers.o(i.__scatterload_zeroinit)
main 0x0800033d Thumb Code 14 main.o(i.main)
Region$$Table$$Base 0x08000350 Number 0 anon$$obj.o(Region$$Table)
Region$$Table$$Limit 0x08000360 Number 0 anon$$obj.o(Region$$Table)
__initial_sp 0x20000200 Data 0 keil_startup_hk32f030m.o(STACK)
==============================================================================
Memory Map of the image
Image Entry point : 0x080000c1
Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00000360, Max: 0x00004000, ABSOLUTE)
Execution Region ER_IROM1 (Base: 0x08000000, Size: 0x00000360, Max: 0x00004000, ABSOLUTE)
Base Addr Size Type Attr Idx E Section Name Object
0x08000000 0x000000c0 Data RO 2648 RESET keil_startup_hk32f030m.o
0x080000c0 0x00000000 Code RO 2653 * .ARM.Collect$$$$00000000 mc_p.l(entry.o)
0x080000c0 0x00000004 Code RO 2658 .ARM.Collect$$$$00000001 mc_p.l(entry2.o)
0x080000c4 0x00000004 Code RO 2661 .ARM.Collect$$$$00000004 mc_p.l(entry5.o)
0x080000c8 0x00000000 Code RO 2663 .ARM.Collect$$$$00000008 mc_p.l(entry7b.o)
0x080000c8 0x00000000 Code RO 2665 .ARM.Collect$$$$0000000A mc_p.l(entry8b.o)
0x080000c8 0x00000008 Code RO 2666 .ARM.Collect$$$$0000000B mc_p.l(entry9a.o)
0x080000d0 0x00000000 Code RO 2668 .ARM.Collect$$$$0000000D mc_p.l(entry10a.o)
0x080000d0 0x00000000 Code RO 2670 .ARM.Collect$$$$0000000F mc_p.l(entry11a.o)
0x080000d0 0x00000004 Code RO 2659 .ARM.Collect$$$$00002712 mc_p.l(entry2.o)
0x080000d4 0x0000001c Code RO 2649 .text keil_startup_hk32f030m.o
0x080000f0 0x00000024 Code RO 2672 .text mc_p.l(init.o)
0x08000114 0x00000084 Code RO 803 i.GPIO_Init hk32f030m_gpio.o
0x08000198 0x00000004 Code RO 811 i.GPIO_SetBits hk32f030m_gpio.o
0x0800019c 0x00000002 Code RO 3 i.HardFault_Handler hk32f030m_it.o
0x0800019e 0x00000002 PAD
0x080001a0 0x00000064 Code RO 168 i.LED_GPIO_Config bsp_led.o
0x08000204 0x00000002 Code RO 4 i.NMI_Handler hk32f030m_it.o
0x08000206 0x00000002 Code RO 5 i.PendSV_Handler hk32f030m_it.o
0x08000208 0x00000018 Code RO 1315 i.RCC_AHBPeriphClockCmd hk32f030m_rcc.o
0x08000220 0x00000002 Code RO 6 i.SVC_Handler hk32f030m_it.o
0x08000222 0x00000002 PAD
0x08000224 0x00000098 Code RO 2610 i.SetSysClockToHSI_32M system_hk32f030m.o
0x080002bc 0x00000002 Code RO 7 i.SysTick_Handler hk32f030m_it.o
0x080002be 0x00000002 PAD
0x080002c0 0x0000005c Code RO 2612 i.SystemInit system_hk32f030m.o
0x0800031c 0x0000000e Code RO 2676 i.__scatterload_copy mc_p.l(handlers.o)
0x0800032a 0x00000002 Code RO 2677 i.__scatterload_null mc_p.l(handlers.o)
0x0800032c 0x0000000e Code RO 2678 i.__scatterload_zeroinit mc_p.l(handlers.o)
0x0800033a 0x00000002 PAD
0x0800033c 0x00000014 Code RO 140 i.main main.o
0x08000350 0x00000010 Data RO 2674 Region$$Table anon$$obj.o
Execution Region RW_IRAM1 (Base: 0x20000000, Size: 0x00000200, Max: 0x00000800, ABSOLUTE)
Base Addr Size Type Attr Idx E Section Name Object
0x20000000 0x00000200 Zero RW 2646 STACK keil_startup_hk32f030m.o
==============================================================================
Image component sizes
Code (inc. data) RO Data RW Data ZI Data Debug Object Name
100 8 0 0 0 574 bsp_led.o
136 0 0 0 0 1863 hk32f030m_gpio.o
10 0 0 0 0 162939 hk32f030m_it.o
24 6 0 0 0 1200 hk32f030m_rcc.o
28 8 192 0 512 704 keil_startup_hk32f030m.o
20 6 0 0 0 459 main.o
244 30 0 0 0 2209 system_hk32f030m.o
----------------------------------------------------------------------
568 58 208 0 512 169948 Object Totals
0 0 16 0 0 0 (incl. Generated)
6 0 0 0 0 0 (incl. Padding)
----------------------------------------------------------------------
Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name
0 0 0 0 0 0 entry.o
0 0 0 0 0 0 entry10a.o
0 0 0 0 0 0 entry11a.o
8 4 0 0 0 0 entry2.o
4 0 0 0 0 0 entry5.o
0 0 0 0 0 0 entry7b.o
0 0 0 0 0 0 entry8b.o
8 4 0 0 0 0 entry9a.o
30 0 0 0 0 0 handlers.o
36 8 0 0 0 68 init.o
----------------------------------------------------------------------
88 16 0 0 0 68 Library Totals
2 0 0 0 0 0 (incl. Padding)
----------------------------------------------------------------------
Code (inc. data) RO Data RW Data ZI Data Debug Library Name
86 16 0 0 0 68 mc_p.l
----------------------------------------------------------------------
88 16 0 0 0 68 Library Totals
----------------------------------------------------------------------
==============================================================================
Code (inc. data) RO Data RW Data ZI Data Debug
656 74 208 0 512 169860 Grand Totals
656 74 208 0 512 169860 ELF Image Totals
656 74 208 0 0 0 ROM Totals
==============================================================================
Total RO Size (Code + RO Data) 864 ( 0.84kB)
Total RW Size (RW Data + ZI Data) 512 ( 0.50kB)
Total ROM Size (Code + RO Data + RW Data) 864 ( 0.84kB)
==============================================================================

View File

@ -0,0 +1,890 @@
ARM Macro Assembler Page 1
1 00000000 ;******************** (C) COPYRIGHT HKMicroChip ******
**************
2 00000000 ;* File Name : KEIL_Startup_hk32f030m.s
3 00000000 ;* Author : MCD Application Team
4 00000000 ;* Description : hk32f030m devices vector table f
or MDK-ARM toolchain.
5 00000000 ;* This module performs:
6 00000000 ;* - Set the initial SP
7 00000000 ;* - Set the initial PC == Reset_Ha
ndler
8 00000000 ;* - Set the vector table entries w
ith the exceptions ISR address
9 00000000 ;* - Branches to __main in the C li
brary (which eventually
10 00000000 ;* calls main()).
11 00000000 ;* After Reset the CortexM0 process
or is in Thread mode,
12 00000000 ;* priority is Privileged, and the
Stack is set to Main.
13 00000000 ;* <<< Use Configuration Wizard in Context Menu >>>
14 00000000 ;*******************************************************
************************
15 00000000
16 00000000 ; Amount of memory (in bytes) allocated for Stack
17 00000000 ; Tailor this value to your application needs
18 00000000 ; <h> Stack Configuration
19 00000000 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
20 00000000 ; </h>
21 00000000
22 00000000 00000200
Stack_Size
EQU 0x00000200
23 00000000
24 00000000 AREA STACK, NOINIT, READWRITE, ALIGN
=3
25 00000000 Stack_Mem
SPACE Stack_Size
26 00000200 __initial_sp
27 00000200
28 00000200
29 00000200 ; <h> Heap Configuration
30 00000200 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
31 00000200 ; </h>
32 00000200
33 00000200 00000200
Heap_Size
EQU 0x00000200
34 00000200
35 00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=
3
36 00000000 __heap_base
37 00000000 Heap_Mem
SPACE Heap_Size
38 00000200 __heap_limit
39 00000200
40 00000200 PRESERVE8
41 00000200 THUMB
42 00000200
43 00000200
ARM Macro Assembler Page 2
44 00000200 ; Vector Table Mapped to Address 0 at Reset
45 00000200 AREA RESET, DATA, READONLY
46 00000000 EXPORT __Vectors
47 00000000 EXPORT __Vectors_End
48 00000000 EXPORT __Vectors_Size
49 00000000
50 00000000 00000000
__Vectors
DCD __initial_sp ; Top of Stack
51 00000004 00000000 DCD Reset_Handler ; Reset Handler
52 00000008 00000000 DCD NMI_Handler ; NMI Handler
53 0000000C 00000000 DCD HardFault_Handler ; Hard Fault
Handler
54 00000010 00000000 DCD 0 ; Reserved
55 00000014 00000000 DCD 0 ; Reserved
56 00000018 00000000 DCD 0 ; Reserved
57 0000001C 00000000 DCD 0 ; Reserved
58 00000020 00000000 DCD 0 ; Reserved
59 00000024 00000000 DCD 0 ; Reserved
60 00000028 00000000 DCD 0 ; Reserved
61 0000002C 00000000 DCD SVC_Handler ; SVCall Handler
62 00000030 00000000 DCD 0 ; Reserved
63 00000034 00000000 DCD 0 ; Reserved
64 00000038 00000000 DCD PendSV_Handler ; PendSV Handler
65 0000003C 00000000 DCD SysTick_Handler
; SysTick Handler
66 00000040
67 00000040 ; External Interrupts
68 00000040 00000000 DCD WWDG_IRQHandler
; Window Watchdog
69 00000044 00000000 DCD 0 ; Reserved
70 00000048 00000000 DCD EXTI11_IRQHandler ; EXTI Line 1
1 interrupt(AWU_WKP
)
71 0000004C 00000000 DCD FLASH_IRQHandler ; FLASH
72 00000050 00000000 DCD RCC_IRQHandler ; RCC
73 00000054 00000000 DCD EXTI0_IRQHandler ; EXTI Line 0
74 00000058 00000000 DCD EXTI1_IRQHandler ; EXTI Line 1
75 0000005C 00000000 DCD EXTI2_IRQHandler ; EXTI Line 2
76 00000060 00000000 DCD EXTI3_IRQHandler ; EXTI Line 3
77 00000064 00000000 DCD EXTI4_IRQHandler ; EXTI Line 4
78 00000068 00000000 DCD EXTI5_IRQHandler ; EXTI Line 5
79 0000006C 00000000 DCD TIM1_BRK_IRQHandler ; TIM1 brea
k interrupt
80 00000070 00000000 DCD ADC1_IRQHandler ; ADC1 interrup
t(combined with EXT
I line 8)
81 00000074 00000000 DCD TIM1_UP_TRG_COM_IRQHandler ; TI
M1 Update, Trigger
and Commutation
82 00000078 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu
re Compare
83 0000007C 00000000 DCD TIM2_IRQHandler ; TIM2
ARM Macro Assembler Page 3
84 00000080 00000000 DCD 0 ; Reserved
85 00000084 00000000 DCD TIM6_IRQHandler ; TIM6
86 00000088 00000000 DCD 0 ; Reserved
87 0000008C 00000000 DCD 0 ; Reserved
88 00000090 00000000 DCD 0 ; Reserved
89 00000094 00000000 DCD EXTI6_IRQHandler ; EXTI Line 6
90 00000098 00000000 DCD EXTI7_IRQHandler ; EXTI Line 7
91 0000009C 00000000 DCD I2C1_IRQHandler ; I2C1(combined
with EXTI line 10)
92 000000A0 00000000 DCD 0 ; Reserved
93 000000A4 00000000 DCD SPI1_IRQHandler ; SPI1
94 000000A8 00000000 DCD 0 ; Reserved
95 000000AC 00000000 DCD USART1_IRQHandler ; USART1(comb
ined with EXTI line
9)
96 000000B0 00000000 DCD 0 ; Reserved
97 000000B4 00000000 DCD 0 ; Reserved
98 000000B8 00000000 DCD 0 ; Reserved
99 000000BC 00000000 DCD 0 ; Reserved
100 000000C0
101 000000C0 __Vectors_End
102 000000C0
103 000000C0 000000C0
__Vectors_Size
EQU __Vectors_End - __Vectors
104 000000C0
105 000000C0 AREA |.text|, CODE, READONLY
106 00000000
107 00000000 ; Reset handler routine
108 00000000 Reset_Handler
PROC
109 00000000 EXPORT Reset_Handler [
WEAK]
110 00000000 IMPORT __main
111 00000000 IMPORT SystemInit
112 00000000 4804 LDR R0, =SystemInit
113 00000002 4780 BLX R0
114 00000004 4804 LDR R0, =__main
115 00000006 4700 BX R0
116 00000008 ENDP
117 00000008
118 00000008 ; Dummy Exception Handlers (infinite loops which can be
modified)
119 00000008
120 00000008 NMI_Handler
PROC
121 00000008 EXPORT NMI_Handler
[WEAK]
122 00000008 E7FE B .
123 0000000A ENDP
125 0000000A HardFault_Handler
PROC
126 0000000A EXPORT HardFault_Handler
[WEAK]
127 0000000A E7FE B .
128 0000000C ENDP
129 0000000C SVC_Handler
ARM Macro Assembler Page 4
PROC
130 0000000C EXPORT SVC_Handler
[WEAK]
131 0000000C E7FE B .
132 0000000E ENDP
133 0000000E PendSV_Handler
PROC
134 0000000E EXPORT PendSV_Handler
[WEAK]
135 0000000E E7FE B .
136 00000010 ENDP
137 00000010 SysTick_Handler
PROC
138 00000010 EXPORT SysTick_Handler
[WEAK]
139 00000010 E7FE B .
140 00000012 ENDP
141 00000012
142 00000012 Default_Handler
PROC
143 00000012
144 00000012 EXPORT WWDG_IRQHandler
[WEAK]
145 00000012 EXPORT EXTI11_IRQHandler
[WEAK]
146 00000012 EXPORT FLASH_IRQHandler
[WEAK]
147 00000012 EXPORT RCC_IRQHandler
[WEAK]
148 00000012 EXPORT EXTI0_IRQHandler
[WEAK]
149 00000012 EXPORT EXTI1_IRQHandler
[WEAK]
150 00000012 EXPORT EXTI2_IRQHandler
[WEAK]
151 00000012 EXPORT EXTI3_IRQHandler
[WEAK]
152 00000012 EXPORT EXTI4_IRQHandler
[WEAK]
153 00000012 EXPORT EXTI5_IRQHandler
[WEAK]
154 00000012 EXPORT TIM1_BRK_IRQHandler
[WEAK]
155 00000012 EXPORT ADC1_IRQHandler
[WEAK]
156 00000012 EXPORT TIM1_UP_TRG_COM_IRQHandler
[WEAK]
157 00000012 EXPORT TIM1_CC_IRQHandler
[WEAK]
158 00000012 EXPORT TIM2_IRQHandler
[WEAK]
159 00000012 EXPORT TIM6_IRQHandler
[WEAK]
160 00000012 EXPORT EXTI6_IRQHandler
[WEAK]
161 00000012 EXPORT EXTI7_IRQHandler
[WEAK]
162 00000012 EXPORT I2C1_IRQHandler
[WEAK]
ARM Macro Assembler Page 5
163 00000012 EXPORT SPI1_IRQHandler
[WEAK]
164 00000012 EXPORT USART1_IRQHandler
[WEAK]
165 00000012
166 00000012 WWDG_IRQHandler
167 00000012 EXTI11_IRQHandler
168 00000012 FLASH_IRQHandler
169 00000012 RCC_IRQHandler
170 00000012 EXTI0_IRQHandler
171 00000012 EXTI1_IRQHandler
172 00000012 EXTI2_IRQHandler
173 00000012 EXTI3_IRQHandler
174 00000012 EXTI4_IRQHandler
175 00000012 EXTI5_IRQHandler
176 00000012 TIM1_BRK_IRQHandler
177 00000012 ADC1_IRQHandler
178 00000012 TIM1_UP_TRG_COM_IRQHandler
179 00000012 TIM1_CC_IRQHandler
180 00000012 TIM2_IRQHandler
181 00000012 TIM6_IRQHandler
182 00000012 EXTI6_IRQHandler
183 00000012 EXTI7_IRQHandler
184 00000012 I2C1_IRQHandler
185 00000012 SPI1_IRQHandler
186 00000012 USART1_IRQHandler
187 00000012
188 00000012
189 00000012 E7FE B .
190 00000014
191 00000014 ENDP
192 00000014
193 00000014 ALIGN
194 00000014
195 00000014 ;*******************************************************
************************
196 00000014 ; User Stack and Heap initialization
197 00000014 ;*******************************************************
************************
198 00000014 IF :DEF:__MICROLIB
199 00000014
200 00000014 EXPORT __initial_sp
201 00000014 EXPORT __heap_base
202 00000014 EXPORT __heap_limit
203 00000014
204 00000014 ELSE
219 ENDIF
220 00000014
221 00000014 END
00000000
00000000
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --apcs=interw
ork --depend=.\objects\keil_startup_hk32f030m.d -o.\objects\keil_startup_hk32f0
30m.o -I"C:\Users\陈逸凡1\Desktop\02 GPIO输出-使用固件库点亮LED灯2022-07-06\Pro
ject\RTE" -IC:\Keil_v5\ARM\CMSIS\Include --predefine="__EVAL SETA 1" --predefin
e="__MICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 521" --list=.\listing
s\keil_startup_hk32f030m.lst ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_St
artup_hk32f030m.s
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
STACK 00000000
Symbol: STACK
Definitions
At line 24 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
Uses
None
Comment: STACK unused
Stack_Mem 00000000
Symbol: Stack_Mem
Definitions
At line 25 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
Uses
None
Comment: Stack_Mem unused
__initial_sp 00000200
Symbol: __initial_sp
Definitions
At line 26 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
Uses
At line 50 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 200 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
3 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
HEAP 00000000
Symbol: HEAP
Definitions
At line 35 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
Uses
None
Comment: HEAP unused
Heap_Mem 00000000
Symbol: Heap_Mem
Definitions
At line 37 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
Uses
None
Comment: Heap_Mem unused
__heap_base 00000000
Symbol: __heap_base
Definitions
At line 36 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
Uses
At line 201 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Comment: __heap_base used once
__heap_limit 00000200
Symbol: __heap_limit
Definitions
At line 38 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
Uses
At line 202 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Comment: __heap_limit used once
4 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
RESET 00000000
Symbol: RESET
Definitions
At line 45 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
Uses
None
Comment: RESET unused
__Vectors 00000000
Symbol: __Vectors
Definitions
At line 50 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
Uses
At line 46 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 103 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
__Vectors_End 000000C0
Symbol: __Vectors_End
Definitions
At line 101 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 47 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 103 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
3 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.text 00000000
Symbol: .text
Definitions
At line 105 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
None
Comment: .text unused
ADC1_IRQHandler 00000012
Symbol: ADC1_IRQHandler
Definitions
At line 177 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 80 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 155 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Default_Handler 00000012
Symbol: Default_Handler
Definitions
At line 142 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
None
Comment: Default_Handler unused
EXTI0_IRQHandler 00000012
Symbol: EXTI0_IRQHandler
Definitions
At line 170 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 73 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 148 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
EXTI11_IRQHandler 00000012
Symbol: EXTI11_IRQHandler
Definitions
At line 167 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 70 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 145 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
EXTI1_IRQHandler 00000012
Symbol: EXTI1_IRQHandler
Definitions
At line 171 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
ARM Macro Assembler Page 2 Alphabetic symbol ordering
Relocatable symbols
up_hk32f030m.s
Uses
At line 74 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 149 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
EXTI2_IRQHandler 00000012
Symbol: EXTI2_IRQHandler
Definitions
At line 172 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 75 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 150 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
EXTI3_IRQHandler 00000012
Symbol: EXTI3_IRQHandler
Definitions
At line 173 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 76 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 151 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
EXTI4_IRQHandler 00000012
Symbol: EXTI4_IRQHandler
Definitions
At line 174 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 77 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 152 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
EXTI5_IRQHandler 00000012
Symbol: EXTI5_IRQHandler
Definitions
At line 175 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 78 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 153 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
EXTI6_IRQHandler 00000012
Symbol: EXTI6_IRQHandler
Definitions
ARM Macro Assembler Page 3 Alphabetic symbol ordering
Relocatable symbols
At line 182 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 89 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 160 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
EXTI7_IRQHandler 00000012
Symbol: EXTI7_IRQHandler
Definitions
At line 183 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 90 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 161 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
FLASH_IRQHandler 00000012
Symbol: FLASH_IRQHandler
Definitions
At line 168 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 71 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 146 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
HardFault_Handler 0000000A
Symbol: HardFault_Handler
Definitions
At line 125 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 53 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 126 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
I2C1_IRQHandler 00000012
Symbol: I2C1_IRQHandler
Definitions
At line 184 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 91 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 162 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
NMI_Handler 00000008
Symbol: NMI_Handler
ARM Macro Assembler Page 4 Alphabetic symbol ordering
Relocatable symbols
Definitions
At line 120 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 52 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 121 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
PendSV_Handler 0000000E
Symbol: PendSV_Handler
Definitions
At line 133 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 64 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 134 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
RCC_IRQHandler 00000012
Symbol: RCC_IRQHandler
Definitions
At line 169 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 72 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 147 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Reset_Handler 00000000
Symbol: Reset_Handler
Definitions
At line 108 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 51 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 109 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
SPI1_IRQHandler 00000012
Symbol: SPI1_IRQHandler
Definitions
At line 185 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 93 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 163 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
SVC_Handler 0000000C
ARM Macro Assembler Page 5 Alphabetic symbol ordering
Relocatable symbols
Symbol: SVC_Handler
Definitions
At line 129 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 61 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 130 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
SysTick_Handler 00000010
Symbol: SysTick_Handler
Definitions
At line 137 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 65 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 138 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
TIM1_BRK_IRQHandler 00000012
Symbol: TIM1_BRK_IRQHandler
Definitions
At line 176 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 79 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 154 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
TIM1_CC_IRQHandler 00000012
Symbol: TIM1_CC_IRQHandler
Definitions
At line 179 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 82 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 157 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
TIM1_UP_TRG_COM_IRQHandler 00000012
Symbol: TIM1_UP_TRG_COM_IRQHandler
Definitions
At line 178 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 81 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 156 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
TIM2_IRQHandler 00000012
ARM Macro Assembler Page 6 Alphabetic symbol ordering
Relocatable symbols
Symbol: TIM2_IRQHandler
Definitions
At line 180 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 83 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 158 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
TIM6_IRQHandler 00000012
Symbol: TIM6_IRQHandler
Definitions
At line 181 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 85 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 159 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
USART1_IRQHandler 00000012
Symbol: USART1_IRQHandler
Definitions
At line 186 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 95 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 164 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
WWDG_IRQHandler 00000012
Symbol: WWDG_IRQHandler
Definitions
At line 166 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 68 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
At line 144 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
29 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Absolute symbols
Heap_Size 00000200
Symbol: Heap_Size
Definitions
At line 33 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
Uses
At line 37 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
Comment: Heap_Size used once
Stack_Size 00000200
Symbol: Stack_Size
Definitions
At line 22 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
Uses
At line 25 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
Comment: Stack_Size used once
__Vectors_Size 000000C0
Symbol: __Vectors_Size
Definitions
At line 103 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 48 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Startu
p_hk32f030m.s
Comment: __Vectors_Size used once
3 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
External symbols
SystemInit 00000000
Symbol: SystemInit
Definitions
At line 111 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 112 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Comment: SystemInit used once
__main 00000000
Symbol: __main
Definitions
At line 110 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Uses
At line 114 in file ..\Source\Libraries\CMSIS\HK32F030M\Source\KEIL_Start
up_hk32f030m.s
Comment: __main used once
2 symbols
379 symbols in table

BIN
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<pre>
<h1>礦ision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: μVision V5.21.1.0
Copyright (C) 2016 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: leon 陈逸凡1, 1, LIC=----
Tool Versions:
Toolchain: MDK-Lite Version: 5.21a
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 3 (build 300)
Assembler: Armasm.exe V5.06 update 3 (build 300)
Linker/Locator: ArmLink.exe V5.06 update 3 (build 300)
Library Manager: ArmAr.exe V5.06 update 3 (build 300)
Hex Converter: FromElf.exe V5.06 update 3 (build 300)
CPU DLL: SARMCM3.DLL V5.21a
Dialog DLL: DARMCM1.DLL V1.14.0.0
Target DLL: Segger\JL2CM3.dll V2.99.23.0
Dialog DLL: TARMCM1.DLL V1.10.0.0
<h2>Project:</h2>
C:\Users\陈逸凡1\Desktop\02 GPIO输出-使用固件库点亮LED灯2022-07-06\Project\Project.uvprojx
Project File Date: 01/07/2023
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 3 (build 300)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Build target 'HK32F030MF4P6'
compiling main.c...
linking...
Program Size: Code=656 RO-data=208 RW-data=0 ZI-data=512
FromELF: creating hex file...
".\Objects\Project.axf" - 0 Error(s), 0 Warning(s).
<h2>Collection of Component include folders:</h2>
C:\Users\陈逸凡1\Desktop\02 GPIO输出-使用固件库点亮LED灯2022-07-06\Project\RTE
<h2>Collection of Component Files used:</h2>
Build Time Elapsed: 00:00:00
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:020000040800F2
:1000000000020020D5000008050200089D0100083C
:1000100000000000000000000000000000000000E0
:1000200000000000000000000000000021020008A5
:10003000000000000000000007020008BD020008E8
:10004000E700000800000000E7000008E7000008E3
:10005000E7000008E7000008E7000008E7000008E4
:10006000E7000008E7000008E7000008E7000008D4
:10007000E7000008E7000008E7000008E7000008C4
:1000800000000000E7000008000000000000000081
:1000900000000000E7000008E7000008E700000893
:1000A00000000000E700000800000000E700000872
:1000B0000000000000000000000000000000000040
:1000C0000348854600F014F8004800473D03000847
:1000D000000200200448804704480047FEE7FEE78E
:1000E000FEE7FEE7FEE7FEE7C1020008C1000008E8
:1000F000064C0125064E05E0E36807CC2B430C3C7B
:1001000098471034B442F7D3FFF7DEFF50030008DE
:1001100060030008F0B50022012423460D689340D7
:100120001D409D422BD10D79012D01D0022D13D1FF
:10013000876855000326AE40B74387604E79AE40CE
:1001400085682E43866045689D43456043688D7988
:100150009540ADB22B434360066855000323AB4086
:100160009E4306600E790768AE403E430660C6684F
:100170009E43C660CB79AB40C5682B43C360521C1D
:10018000102ACAD30A7A002A026B096802D08A436D
:100190000263F0BD0A43FBE781617047FEE70000A0
:1001A000FEB50D200121400400F02EF80220009041
:1001B00001206946087100228A71104C487120465E
:1001C000FFF7A8FF80200E4D009069462846FFF7F4
:1001D000A1FF04200926F606009069463046FFF785
:1001E00099FF02212046FFF7D7FF80212846FFF71D
:1001F000D3FF04213046FFF7CFFFFEBD000C0048BF
:100200000008004870477047044A0029516901D02E
:10021000014300E08143516170470000001002403B
:10022000704700003CB5002221480092019201680D
:100230000123194301601E49C0318C6A0F25ED026C
:10024000AC438C628C6A0725ED022C438C62194CFE
:10025000022105680D400195009D6D1C0095019DD2
:10026000002D02D1009DA542F3D10468A4071DD53D
:10027000114A01931368DB08DB0001930B43136001
:100280004168F022914301914160416807221202C6
:10029000914301914160416889088900416041684A
:1002A000416041680907890FFBD13CBD01923CBD0B
:1002B00000100240FFFF00000020024070470000D5
:1002C00010B5124801680122114301604168104ACB
:1002D00011404160016B132291430163002484604B
:1002E0000C49096A0A0C89B20A4209D10268CA0695
:1002F0004905120E890E09020A4301681143016083
:10030000FFF790FF0448446310BD00000010024056
:100310001CB8FFF800F8FF1F4020024002E008C8A8
:10032000121F08C1002AFAD170477047002001E06F
:1003300001C1121F002AFBD170470000FFF730FFF8
:100340000248802181628161FCE7000000080048CA
:100350006003000800000020000200002C030008D9
:04000005080000C12E
:00000001FF

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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html><head>
<title>Static Call Graph - [.\Objects\Project.axf]</title></head>
<body><HR>
<H1>Static Call Graph for image .\Objects\Project.axf</H1><HR>
<BR><P>#&#060CALLGRAPH&#062# ARM Linker, 5060300: Last Updated: Sat Jan 07 22:52:57 2023
<BR><P>
<H3>Maximum Stack Usage = 52 bytes + Unknown(Cycles, Untraceable Function Pointers)</H3><H3>
Call chain for Maximum Stack Depth:</H3>
main &rArr; LED_GPIO_Config &rArr; GPIO_Init
<P>
<H3>
Mutually Recursive functions
</H3> <LI><a href="#[11]">ADC1_IRQHandler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[11]">ADC1_IRQHandler</a><BR>
<LI><a href="#[2]">HardFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[2]">HardFault_Handler</a><BR>
</UL>
<P>
<H3>
Function Pointers
</H3><UL>
<LI><a href="#[11]">ADC1_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[a]">EXTI0_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[7]">EXTI11_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[b]">EXTI1_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[c]">EXTI2_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[d]">EXTI3_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[e]">EXTI4_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[f]">EXTI5_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[16]">EXTI6_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[17]">EXTI7_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[8]">FLASH_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[2]">HardFault_Handler</a> from hk32f030m_it.o(i.HardFault_Handler) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[18]">I2C1_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[1]">NMI_Handler</a> from hk32f030m_it.o(i.NMI_Handler) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[4]">PendSV_Handler</a> from hk32f030m_it.o(i.PendSV_Handler) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[9]">RCC_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[0]">Reset_Handler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[19]">SPI1_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[3]">SVC_Handler</a> from hk32f030m_it.o(i.SVC_Handler) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[5]">SysTick_Handler</a> from hk32f030m_it.o(i.SysTick_Handler) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[1c]">SystemInit</a> from system_hk32f030m.o(i.SystemInit) referenced from keil_startup_hk32f030m.o(.text)
<LI><a href="#[10]">TIM1_BRK_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[13]">TIM1_CC_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[12]">TIM1_UP_TRG_COM_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[14]">TIM2_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[15]">TIM6_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[1a]">USART1_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[6]">WWDG_IRQHandler</a> from keil_startup_hk32f030m.o(.text) referenced from keil_startup_hk32f030m.o(RESET)
<LI><a href="#[1d]">__main</a> from entry.o(.ARM.Collect$$$$00000000) referenced from keil_startup_hk32f030m.o(.text)
<LI><a href="#[1b]">main</a> from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
</UL>
<P>
<H3>
Global Symbols
</H3>
<P><STRONG><a name="[1d]"></a>__main</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(.text)
</UL>
<P><STRONG><a name="[26]"></a>_main_stk</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
<P><STRONG><a name="[1e]"></a>_main_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
<BR><BR>[Calls]<UL><LI><a href="#[1f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
</UL>
<P><STRONG><a name="[20]"></a>__main_after_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
<BR><BR>[Called By]<UL><LI><a href="#[1f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
</UL>
<P><STRONG><a name="[27]"></a>_main_clock</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
<P><STRONG><a name="[28]"></a>_main_cpp_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
<P><STRONG><a name="[29]"></a>_main_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
<P><STRONG><a name="[2a]"></a>__rt_final_cpp</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D))
<P><STRONG><a name="[2b]"></a>__rt_final_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F))
<P><STRONG><a name="[0]"></a>Reset_Handler</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[11]"></a>ADC1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[11]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC1_IRQHandler
</UL>
<BR>[Called By]<UL><LI><a href="#[11]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC1_IRQHandler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[a]"></a>EXTI0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[7]"></a>EXTI11_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[b]"></a>EXTI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[c]"></a>EXTI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[d]"></a>EXTI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[e]"></a>EXTI4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[f]"></a>EXTI5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[16]"></a>EXTI6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[17]"></a>EXTI7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[8]"></a>FLASH_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[18]"></a>I2C1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[9]"></a>RCC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[19]"></a>SPI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[10]"></a>TIM1_BRK_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[13]"></a>TIM1_CC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[12]"></a>TIM1_UP_TRG_COM_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[14]"></a>TIM2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[15]"></a>TIM6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[1a]"></a>USART1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[6]"></a>WWDG_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, keil_startup_hk32f030m.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[1f]"></a>__scatterload</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[20]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__main_after_scatterload
</UL>
<BR>[Called By]<UL><LI><a href="#[1e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_main_scatterload
</UL>
<P><STRONG><a name="[2c]"></a>__scatterload_rt2</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
<P><STRONG><a name="[23]"></a>GPIO_Init</STRONG> (Thumb, 132 bytes, Stack size 20 bytes, hk32f030m_gpio.o(i.GPIO_Init))
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = GPIO_Init
</UL>
<BR>[Called By]<UL><LI><a href="#[21]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;LED_GPIO_Config
</UL>
<P><STRONG><a name="[24]"></a>GPIO_SetBits</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, hk32f030m_gpio.o(i.GPIO_SetBits))
<BR><BR>[Called By]<UL><LI><a href="#[21]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;LED_GPIO_Config
</UL>
<P><STRONG><a name="[2]"></a>HardFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, hk32f030m_it.o(i.HardFault_Handler))
<BR><BR>[Calls]<UL><LI><a href="#[2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[21]"></a>LED_GPIO_Config</STRONG> (Thumb, 92 bytes, Stack size 32 bytes, bsp_led.o(i.LED_GPIO_Config))
<BR><BR>[Stack]<UL><LI>Max Depth = 52<LI>Call Chain = LED_GPIO_Config &rArr; GPIO_Init
</UL>
<BR>[Calls]<UL><LI><a href="#[22]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;RCC_AHBPeriphClockCmd
<LI><a href="#[24]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_SetBits
<LI><a href="#[23]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_Init
</UL>
<BR>[Called By]<UL><LI><a href="#[1b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<P><STRONG><a name="[1]"></a>NMI_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, hk32f030m_it.o(i.NMI_Handler))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[4]"></a>PendSV_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, hk32f030m_it.o(i.PendSV_Handler))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[22]"></a>RCC_AHBPeriphClockCmd</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, hk32f030m_rcc.o(i.RCC_AHBPeriphClockCmd))
<BR><BR>[Called By]<UL><LI><a href="#[21]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;LED_GPIO_Config
</UL>
<P><STRONG><a name="[3]"></a>SVC_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, hk32f030m_it.o(i.SVC_Handler))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[5]"></a>SysTick_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, hk32f030m_it.o(i.SysTick_Handler))
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(RESET)
</UL>
<P><STRONG><a name="[1c]"></a>SystemInit</STRONG> (Thumb, 74 bytes, Stack size 8 bytes, system_hk32f030m.o(i.SystemInit))
<BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = SystemInit &rArr; SetSysClockToHSI_32M
</UL>
<BR>[Calls]<UL><LI><a href="#[25]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SetSysClockToHSI_32M
</UL>
<BR>[Address Reference Count : 1]<UL><LI> keil_startup_hk32f030m.o(.text)
</UL>
<P><STRONG><a name="[2d]"></a>__scatterload_copy</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
<P><STRONG><a name="[2e]"></a>__scatterload_null</STRONG> (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
<P><STRONG><a name="[2f]"></a>__scatterload_zeroinit</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
<P><STRONG><a name="[1b]"></a>main</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, main.o(i.main))
<BR><BR>[Stack]<UL><LI>Max Depth = 52<LI>Call Chain = main &rArr; LED_GPIO_Config &rArr; GPIO_Init
</UL>
<BR>[Calls]<UL><LI><a href="#[21]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;LED_GPIO_Config
</UL>
<BR>[Address Reference Count : 1]<UL><LI> entry9a.o(.ARM.Collect$$$$0000000B)
</UL><P>
<H3>
Local Symbols
</H3>
<P><STRONG><a name="[25]"></a>SetSysClockToHSI_32M</STRONG> (Thumb, 140 bytes, Stack size 20 bytes, system_hk32f030m.o(i.SetSysClockToHSI_32M))
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = SetSysClockToHSI_32M
</UL>
<BR>[Called By]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemInit
</UL>
<P>
<H3>
Undefined Global Symbols
</H3><HR></body></html>

View File

@ -0,0 +1,27 @@
--cpu Cortex-M0
".\objects\hk32f030m_it.o"
".\objects\main.o"
".\objects\bsp_led.o"
".\objects\hk32f030m_adc.o"
".\objects\hk32f030m_awu.o"
".\objects\hk32f030m_beep.o"
".\objects\hk32f030m_crc.o"
".\objects\hk32f030m_exti.o"
".\objects\hk32f030m_flash.o"
".\objects\hk32f030m_gpio.o"
".\objects\hk32f030m_i2c.o"
".\objects\hk32f030m_iwdg.o"
".\objects\hk32f030m_misc.o"
".\objects\hk32f030m_pwr.o"
".\objects\hk32f030m_rcc.o"
".\objects\hk32f030m_spi.o"
".\objects\hk32f030m_syscfg.o"
".\objects\hk32f030m_tim.o"
".\objects\hk32f030m_usart.o"
".\objects\hk32f030m_wwdg.o"
".\objects\system_hk32f030m.o"
".\objects\keil_startup_hk32f030m.o"
--library_type=microlib --strict --scatter ".\Objects\Project.sct"
--summary_stderr --info summarysizes --map --xref --callgraph --symbols
--info sizes --info totals --info unused --info veneers
--list ".\Listings\Project.map" -o .\Objects\Project.axf

View File

@ -0,0 +1,15 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00004000 { ; load region size_region
ER_IROM1 0x08000000 0x00004000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00000800 { ; RW data
.ANY (+RW +ZI)
}
}

View File

@ -0,0 +1,595 @@
Dependencies for Project 'Project', Target 'HK32F030MF4P6': (DO NOT MODIFY !)
F (..\Source\User\hk32f030m_it.c)(0x5E95B54E)(--c99 -c --cpu Cortex-M0 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Source\Libraries\HK32F030M_Lib\inc -I ..\Source\Libraries\HK32F030M_Lib\src -I ..\Source\Libraries\CMSIS\CM0\Core -I ..\Source\Libraries\CMSIS\CM0 -I ..\Source\Libraries\CMSIS\HK32F030M\Include -I ..\Source\Libraries\CMSIS\HK32F030M\Source -I ..\Source\User -I ..\Source\User\led -I"C:\Users\陈逸凡1\Desktop\02 GPIO输出-使用固件库点亮LED灯2022-07-06\Project\RTE" -IC:\Keil_v5\ARM\CMSIS\Include -D__UVISION_VERSION="521" -DHK32F030M -DHK32F030MF4P6 -o .\objects\hk32f030m_it.o --omf_browse .\objects\hk32f030m_it.crf --depend .\objects\hk32f030m_it.d)
I (..\Source\User\main.h)(0x62B47CDE)
I (..\Source\User\hk32f030m_it.h)(0x5E5DD682)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_tim.h)(0x5E5DD07A)
I (..\Source\Libraries\CMSIS\HK32F030M\Include\hk32f030m.h)(0x5F5AEBB6)
I (..\Source\Libraries\CMSIS\CM0\Core\core_cm0.h)(0x5D1337BA)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x574E3E26)
I (..\Source\Libraries\CMSIS\CM0\Core\core_cmInstr.h)(0x5D1337BA)
I (..\Source\Libraries\CMSIS\CM0\Core\cmsis_armcc.h)(0x5D1337BA)
I (..\Source\Libraries\CMSIS\CM0\Core\core_cmFunc.h)(0x5D1337BA)
I (..\Source\Libraries\CMSIS\HK32F030M\Include\system_hk32f030m.h)(0x5E5DC2BE)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_def.h)(0x5E6A11A4)
I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x574E3E26)
I (..\Source\User\hk32f030m_conf.h)(0x5E661B6A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_rcc.h)(0x5E6A1246)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_crc.h)(0x5E5DCD84)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_exti.h)(0x5E5DCD9E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_flash.h)(0x5EBA7DC8)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_gpio.h)(0x5F36298A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_misc.h)(0x5E5DCF30)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_adc.h)(0x5E5DC35E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_syscfg.h)(0x5F5AEE22)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_i2c.h)(0x5E6A11EE)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_iwdg.h)(0x5E5DCF08)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_pwr.h)(0x5E65BD6A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_spi.h)(0x5E5E1518)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_usart.h)(0x5E6A127E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_wwdg.h)(0x5E5DD1BC)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_awu.h)(0x5E5DC37E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_beep.h)(0x5E787614)
F (..\Source\User\main.c)(0x63B98745)(--c99 -c --cpu Cortex-M0 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Source\Libraries\HK32F030M_Lib\inc -I ..\Source\Libraries\HK32F030M_Lib\src -I ..\Source\Libraries\CMSIS\CM0\Core -I ..\Source\Libraries\CMSIS\CM0 -I ..\Source\Libraries\CMSIS\HK32F030M\Include -I ..\Source\Libraries\CMSIS\HK32F030M\Source -I ..\Source\User -I ..\Source\User\led -I"C:\Users\陈逸凡1\Desktop\02 GPIO输出-使用固件库点亮LED灯2022-07-06\Project\RTE" -IC:\Keil_v5\ARM\CMSIS\Include -D__UVISION_VERSION="521" -DHK32F030M -DHK32F030MF4P6 -o .\objects\main.o --omf_browse .\objects\main.crf --depend .\objects\main.d)
I (..\Source\Libraries\CMSIS\HK32F030M\Include\hk32f030m.h)(0x5F5AEBB6)
I (..\Source\Libraries\CMSIS\CM0\Core\core_cm0.h)(0x5D1337BA)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x574E3E26)
I (..\Source\Libraries\CMSIS\CM0\Core\core_cmInstr.h)(0x5D1337BA)
I (..\Source\Libraries\CMSIS\CM0\Core\cmsis_armcc.h)(0x5D1337BA)
I (..\Source\Libraries\CMSIS\CM0\Core\core_cmFunc.h)(0x5D1337BA)
I (..\Source\Libraries\CMSIS\HK32F030M\Include\system_hk32f030m.h)(0x5E5DC2BE)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_def.h)(0x5E6A11A4)
I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x574E3E26)
I (..\Source\User\hk32f030m_conf.h)(0x5E661B6A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_rcc.h)(0x5E6A1246)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_crc.h)(0x5E5DCD84)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_exti.h)(0x5E5DCD9E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_flash.h)(0x5EBA7DC8)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_gpio.h)(0x5F36298A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_misc.h)(0x5E5DCF30)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_adc.h)(0x5E5DC35E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_syscfg.h)(0x5F5AEE22)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_i2c.h)(0x5E6A11EE)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_iwdg.h)(0x5E5DCF08)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_pwr.h)(0x5E65BD6A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_spi.h)(0x5E5E1518)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_tim.h)(0x5E5DD07A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_usart.h)(0x5E6A127E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_wwdg.h)(0x5E5DD1BC)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_awu.h)(0x5E5DC37E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_beep.h)(0x5E787614)
I (..\Source\User\led\bsp_led.h)(0x62C248A3)
F (..\Source\User\led\bsp_led.c)(0x62C4F5D9)(--c99 -c --cpu Cortex-M0 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Source\Libraries\HK32F030M_Lib\inc -I ..\Source\Libraries\HK32F030M_Lib\src -I ..\Source\Libraries\CMSIS\CM0\Core -I ..\Source\Libraries\CMSIS\CM0 -I ..\Source\Libraries\CMSIS\HK32F030M\Include -I ..\Source\Libraries\CMSIS\HK32F030M\Source -I ..\Source\User -I ..\Source\User\led -I"C:\Users\陈逸凡1\Desktop\02 GPIO输出-使用固件库点亮LED灯2022-07-06\Project\RTE" -IC:\Keil_v5\ARM\CMSIS\Include -D__UVISION_VERSION="521" -DHK32F030M -DHK32F030MF4P6 -o .\objects\bsp_led.o --omf_browse .\objects\bsp_led.crf --depend .\objects\bsp_led.d)
I (..\Source\User\led\bsp_led.h)(0x62C248A3)
I (..\Source\Libraries\CMSIS\HK32F030M\Include\hk32f030m.h)(0x5F5AEBB6)
I (..\Source\Libraries\CMSIS\CM0\Core\core_cm0.h)(0x5D1337BA)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x574E3E26)
I (..\Source\Libraries\CMSIS\CM0\Core\core_cmInstr.h)(0x5D1337BA)
I (..\Source\Libraries\CMSIS\CM0\Core\cmsis_armcc.h)(0x5D1337BA)
I (..\Source\Libraries\CMSIS\CM0\Core\core_cmFunc.h)(0x5D1337BA)
I (..\Source\Libraries\CMSIS\HK32F030M\Include\system_hk32f030m.h)(0x5E5DC2BE)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_def.h)(0x5E6A11A4)
I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x574E3E26)
I (..\Source\User\hk32f030m_conf.h)(0x5E661B6A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_rcc.h)(0x5E6A1246)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_crc.h)(0x5E5DCD84)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_exti.h)(0x5E5DCD9E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_flash.h)(0x5EBA7DC8)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_gpio.h)(0x5F36298A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_misc.h)(0x5E5DCF30)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_adc.h)(0x5E5DC35E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_syscfg.h)(0x5F5AEE22)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_i2c.h)(0x5E6A11EE)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_iwdg.h)(0x5E5DCF08)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_pwr.h)(0x5E65BD6A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_spi.h)(0x5E5E1518)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_tim.h)(0x5E5DD07A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_usart.h)(0x5E6A127E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_wwdg.h)(0x5E5DD1BC)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_awu.h)(0x5E5DC37E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_beep.h)(0x5E787614)
F (..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_adc.c)(0x5EF1CB3E)(--c99 -c --cpu Cortex-M0 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Source\Libraries\HK32F030M_Lib\inc -I ..\Source\Libraries\HK32F030M_Lib\src -I ..\Source\Libraries\CMSIS\CM0\Core -I ..\Source\Libraries\CMSIS\CM0 -I ..\Source\Libraries\CMSIS\HK32F030M\Include -I ..\Source\Libraries\CMSIS\HK32F030M\Source -I ..\Source\User -I ..\Source\User\led -I"C:\Users\陈逸凡1\Desktop\02 GPIO输出-使用固件库点亮LED灯2022-07-06\Project\RTE" -IC:\Keil_v5\ARM\CMSIS\Include -D__UVISION_VERSION="521" -DHK32F030M -DHK32F030MF4P6 -o .\objects\hk32f030m_adc.o --omf_browse .\objects\hk32f030m_adc.crf --depend .\objects\hk32f030m_adc.d)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_adc.h)(0x5E5DC35E)
I (..\Source\Libraries\CMSIS\HK32F030M\Include\hk32f030m.h)(0x5F5AEBB6)
I (..\Source\Libraries\CMSIS\CM0\Core\core_cm0.h)(0x5D1337BA)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x574E3E26)
I (..\Source\Libraries\CMSIS\CM0\Core\core_cmInstr.h)(0x5D1337BA)
I (..\Source\Libraries\CMSIS\CM0\Core\cmsis_armcc.h)(0x5D1337BA)
I (..\Source\Libraries\CMSIS\CM0\Core\core_cmFunc.h)(0x5D1337BA)
I (..\Source\Libraries\CMSIS\HK32F030M\Include\system_hk32f030m.h)(0x5E5DC2BE)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_def.h)(0x5E6A11A4)
I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x574E3E26)
I (..\Source\User\hk32f030m_conf.h)(0x5E661B6A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_rcc.h)(0x5E6A1246)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_crc.h)(0x5E5DCD84)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_exti.h)(0x5E5DCD9E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_flash.h)(0x5EBA7DC8)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_gpio.h)(0x5F36298A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_misc.h)(0x5E5DCF30)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_syscfg.h)(0x5F5AEE22)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_i2c.h)(0x5E6A11EE)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_iwdg.h)(0x5E5DCF08)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_pwr.h)(0x5E65BD6A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_spi.h)(0x5E5E1518)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_tim.h)(0x5E5DD07A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_usart.h)(0x5E6A127E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_wwdg.h)(0x5E5DD1BC)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_awu.h)(0x5E5DC37E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_beep.h)(0x5E787614)
F (..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_awu.c)(0x5E5DD23A)(--c99 -c --cpu Cortex-M0 -D__EVAL -D__MICROLIB -g -O3 --apcs=interwork --split_sections -I ..\Source\Libraries\HK32F030M_Lib\inc -I ..\Source\Libraries\HK32F030M_Lib\src -I ..\Source\Libraries\CMSIS\CM0\Core -I ..\Source\Libraries\CMSIS\CM0 -I ..\Source\Libraries\CMSIS\HK32F030M\Include -I ..\Source\Libraries\CMSIS\HK32F030M\Source -I ..\Source\User -I ..\Source\User\led -I"C:\Users\陈逸凡1\Desktop\02 GPIO输出-使用固件库点亮LED灯2022-07-06\Project\RTE" -IC:\Keil_v5\ARM\CMSIS\Include -D__UVISION_VERSION="521" -DHK32F030M -DHK32F030MF4P6 -o .\objects\hk32f030m_awu.o --omf_browse .\objects\hk32f030m_awu.crf --depend .\objects\hk32f030m_awu.d)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_awu.h)(0x5E5DC37E)
I (..\Source\Libraries\CMSIS\HK32F030M\Include\hk32f030m.h)(0x5F5AEBB6)
I (..\Source\Libraries\CMSIS\CM0\Core\core_cm0.h)(0x5D1337BA)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x574E3E26)
I (..\Source\Libraries\CMSIS\CM0\Core\core_cmInstr.h)(0x5D1337BA)
I (..\Source\Libraries\CMSIS\CM0\Core\cmsis_armcc.h)(0x5D1337BA)
I (..\Source\Libraries\CMSIS\CM0\Core\core_cmFunc.h)(0x5D1337BA)
I (..\Source\Libraries\CMSIS\HK32F030M\Include\system_hk32f030m.h)(0x5E5DC2BE)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_def.h)(0x5E6A11A4)
I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x574E3E26)
I (..\Source\User\hk32f030m_conf.h)(0x5E661B6A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_rcc.h)(0x5E6A1246)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_crc.h)(0x5E5DCD84)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_exti.h)(0x5E5DCD9E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_flash.h)(0x5EBA7DC8)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_gpio.h)(0x5F36298A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_misc.h)(0x5E5DCF30)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_adc.h)(0x5E5DC35E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_syscfg.h)(0x5F5AEE22)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_i2c.h)(0x5E6A11EE)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_iwdg.h)(0x5E5DCF08)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_pwr.h)(0x5E65BD6A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_spi.h)(0x5E5E1518)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_tim.h)(0x5E5DD07A)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_usart.h)(0x5E6A127E)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_wwdg.h)(0x5E5DD1BC)
I (..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_beep.h)(0x5E787614)
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LR_IROM1 0x08000000 0x00004000 { ; load region size_region
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*.o (RESET, +First)
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.\objects\bsp_led.o: ..\Source\User\led\bsp_led.c
.\objects\bsp_led.o: ..\Source\User\led\bsp_led.h
.\objects\bsp_led.o: ..\Source\Libraries\CMSIS\HK32F030M\Include\hk32f030m.h
.\objects\bsp_led.o: ..\Source\Libraries\CMSIS\CM0\Core\core_cm0.h
.\objects\bsp_led.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\bsp_led.o: ..\Source\Libraries\CMSIS\CM0\Core\core_cmInstr.h
.\objects\bsp_led.o: ..\Source\Libraries\CMSIS\CM0\Core\cmsis_armcc.h
.\objects\bsp_led.o: ..\Source\Libraries\CMSIS\CM0\Core\core_cmFunc.h
.\objects\bsp_led.o: ..\Source\Libraries\CMSIS\HK32F030M\Include\system_hk32f030m.h
.\objects\bsp_led.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_def.h
.\objects\bsp_led.o: ..\Source\Libraries\CMSIS\HK32F030M\Include\hk32f030m.h
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.\objects\bsp_led.o: ..\Source\User\hk32f030m_conf.h
.\objects\bsp_led.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_rcc.h
.\objects\bsp_led.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_crc.h
.\objects\bsp_led.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_exti.h
.\objects\bsp_led.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_flash.h
.\objects\bsp_led.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_gpio.h
.\objects\bsp_led.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_misc.h
.\objects\bsp_led.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_adc.h
.\objects\bsp_led.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_syscfg.h
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.\objects\bsp_led.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_pwr.h
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.\objects\hk32f030m_adc.o: ..\Source\Libraries\HK32F030M_Lib\src\hk32f030m_adc.c
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.\objects\hk32f030m_adc.o: ..\Source\Libraries\CMSIS\CM0\Core\cmsis_armcc.h
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.\objects\hk32f030m_adc.o: ..\Source\Libraries\CMSIS\HK32F030M\Include\system_hk32f030m.h
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.\objects\hk32f030m_adc.o: ..\Source\Libraries\CMSIS\HK32F030M\Include\hk32f030m.h
.\objects\hk32f030m_adc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
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.\objects\hk32f030m_adc.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_exti.h
.\objects\hk32f030m_adc.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_flash.h
.\objects\hk32f030m_adc.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_gpio.h
.\objects\hk32f030m_adc.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_misc.h
.\objects\hk32f030m_adc.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_adc.h
.\objects\hk32f030m_adc.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_syscfg.h
.\objects\hk32f030m_adc.o: ..\Source\Libraries\HK32F030M_Lib\inc\hk32f030m_i2c.h
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<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>HK32F030MF4P6</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<nTsel>3</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>CMSIS_AGDI</Key>
<Name>-X"Any" -UAny -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO23 -FD20000000 -FC800 -FN1 -FF0HK32F030MXX_16.FLM -FS08000000 -FL04000 -FP0($$Device:HK32F030MF4P6$Flash\HK32F030MXX_16.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U50121742 -O2126 -S1 -ZTIFSpeedSel10000 -A0 -C0 -JU1 -JI-JP0 -JP0 -RST1 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO31 -FD20000000 -FC800 -FN1 -FF0HK32F030MXX_16.FLM -FS08000000 -FL04000 -FP0($$Device:HK32F030MF4P6$Flash\HK32F030MXX_16.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC800 -FN1 -FF0HK32F030MXX_16 -FS08000000 -FL04000 -FP0($$Device:HK32F030MF4P6$Flash\HK32F030MXX_16.FLM))</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<Lin2Executable></Lin2Executable>
<Lin2ConfigFile></Lin2ConfigFile>
<bLin2Auto>0</bLin2Auto>
</TargetOption>
</Target>
<Group>
<GroupName>User</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Source\User\hk32f030m_it.c</PathWithFileName>
<FilenameWithoutPath>hk32f030m_it.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
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<tvExpOptDlg>0</tvExpOptDlg>
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<PathWithFileName>..\Source\User\led\bsp_led.c</PathWithFileName>
<FilenameWithoutPath>bsp_led.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>StdPeriph_Driver</GroupName>
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<File>
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Project/Project.uvprojx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>HK32F030MF4P6</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060300::V5.06 update 3 (build 300)::ARMCC</pCCUsed>
<TargetOption>
<TargetCommonOption>
<Device>HK32F030MF4P6</Device>
<Vendor>HK_MicroChip</Vendor>
<PackID>HKMicroChip.HK32F030Mxx_DFP.1.0.12</PackID>
<PackURL>http://www.hsxp-hk.com/companyfile/2/</PackURL>
<Cpu>IRAM(0x20000000,0x800) IROM(0x08000000,0x4000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC800 -FN1 -FF0HK32F030MXX_16 -FS08000000 -FL04000 -FP0($$Device:HK32F030MF4P6$Flash\HK32F030MXX_16.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile></RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:HK32F030MF4P6$SVD\HK32F030M.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>Project</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
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<nStopB1X>0</nStopB1X>
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</BeforeMake>
<AfterMake>
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<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
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<nStopA1X>0</nStopA1X>
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</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
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<StartAddress>0x8000000</StartAddress>
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</OCR_RVCT3>
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<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x4000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
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<Type>0</Type>
<StartAddress>0x0</StartAddress>
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</OCR_RVCT6>
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<Type>0</Type>
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</OCR_RVCT7>
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</OCR_RVCT8>
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<StartAddress>0x20000000</StartAddress>
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</OCR_RVCT9>
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</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
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<Define>HK32F030M,HK32F030MF4P6</Define>
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<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
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<Group>
<GroupName>User</GroupName>
<Files>
<File>
<FileName>hk32f030m_it.c</FileName>
<FileType>1</FileType>
<FilePath>..\Source\User\hk32f030m_it.c</FilePath>
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</Project>

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@ -0,0 +1,136 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. October 2015
* $Revision: V.1.4.5 a
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
/* extern const q31_t realCoefAQ31[1024]; */
/* extern const q31_t realCoefBQ31[1024]; */
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */

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@ -0,0 +1,79 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. March 2015
* $Revision: V.1.4.5
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS Cortex-M Core Function/Instruction Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return(result);
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* (__CORTEX_M >= 0x04) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) < 0)
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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@ -0,0 +1,914 @@
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex-M0+
@{
*/
/* CMSIS CM0+ definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000U
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1U)
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1U)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0+ header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) < 0)
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

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@ -0,0 +1,926 @@
/**************************************************************************//**
* @file core_sc000.h
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_SC000_H_GENERIC
#define __CORE_SC000_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup SC000
@{
*/
/* CMSIS SC000 definitions */
#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_SC (000U) /*!< Cortex secure core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC000_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_SC000_H_DEPENDANT
#define __CORE_SC000_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __SC000_REV
#define __SC000_REV 0x0000U
#warning "__SC000_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group SC000 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED0[1U];
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
uint32_t RESERVED1[154U];
__IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the SC000 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of SC000 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) < 0)
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC000_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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