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Bin Meng 5bf0f7f65d x86: galileo: Add PCIe root port IRQ routing 
Now we have enabled PCIe root port on Quark SoC, add its PIRQ
routing information in the device tree as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
 		2015-09-16 19:53:53 -06:00
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include
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microcode x86: baytrail: Add microcode for BayTrail-I D0 stepping 2015-08-26 07:54:09 -07:00
.gitignore
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Makefile x86: dts: Add a device tree file for EFI 2015-08-05 08:44:06 -06:00
bayleybay.dts x86: baytrail: Support multiple microcode copies 2015-08-26 07:54:09 -07:00
chromebook_link.dts exynos: x86: dts: Add tpm nodes to the device tree for Chrome OS devices 2015-08-31 07:57:28 -06:00
chromebox_panther.dts x86: panther: Add PCI and video configuration 2015-09-09 07:48:03 -06:00
crownbay.dts x86: crownbay: Support Topcliff integrated pci uart devices with driver model 2015-08-26 07:54:17 -07:00
efi.dts x86: dts: Add a device tree file for EFI 2015-08-05 08:44:06 -06:00
galileo.dts x86: galileo: Add PCIe root port IRQ routing 2015-09-16 19:53:53 -06:00
minnowmax.dts x86: minnowmax: Correct pad-offset value for host_en1 2015-08-26 07:54:14 -07:00
qemu-x86_i440fx.dts x86: qemu: Add MP initialization 2015-08-05 08:42:38 -06:00
qemu-x86_q35.dts x86: qemu: Add MP initialization 2015-08-05 08:42:38 -06:00
rtc.dtsi x86: Enable DM RTC support for all x86 boards 2015-07-28 10:36:22 -06:00
serial.dtsi x86: Add support for Intel Minnowboard Max 2015-02-06 12:07:39 -07:00
skeleton.dtsi
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