Alexey Brodkin db6ce2312d arc: cache - utilize IO coherency (AKA IOC) engine ... With release of ARC HS38 v2.1 new IO coherency engine could be built-in ARC core. This hardware module ensures coherency between DMA-ed data from peripherals and L2 cache. With L2 and IOC enabled there's no overhead for L2 cache manual maintenance which results in significantly improved IO bandwidth. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>		2016-02-20 11:20:05 +03:00
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arcregs.h	arc: cache - utilize IO coherency (AKA IOC) engine	2016-02-20 11:20:05 +03:00
bitops.h	arc: Use the generic bitops headers	2015-11-05 10:52:29 -05:00
byteorder.h	…
cache.h	arc: cache - accommodate different L1 cache line lengths	2016-02-20 11:19:53 +03:00
config.h	arc: get rid of CONFIG_SYS_GENERIC_GLOBAL_DATA	2015-04-03 09:47:49 +03:00
errno.h	…
global_data.h	…
init_helpers.h	arc: clean-up init procedure	2015-04-03 09:47:49 +03:00
io.h	arc: add stubs for map_physmem() and unmap_physmem()	2015-11-18 00:38:35 +03:00
linkage.h	use ASM_NL instead of '; ' for assembler new line character in the macro	2015-03-05 20:49:43 -05:00
posix_types.h	…
processor.h	arc: add empty asm/processor.h to satisfy compilation of USB code	2015-11-18 00:39:22 +03:00
ptrace.h	…
relocate.h	arc: clean-up init procedure	2015-04-03 09:47:49 +03:00
sections.h	arc: relocate - minor refactoring and clean-up	2015-01-15 22:38:42 +03:00
string.h	…
types.h	…
u-boot-arc.h	arc: clean-up init procedure	2015-04-03 09:47:49 +03:00
u-boot.h	…
unaligned.h	…