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York Sun 379c5145ef powerpc/corenet2: fix mismatch DDR sync bit from RCW 
Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only
async mode is supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
 		2012-10-22 14:31:20 -05:00
..
arm Merge branch 'master' of git://git.denx.de/u-boot-arm 2012-10-19 18:23:38 -07:00
avr32 avr32: Change bi_baudrate and global data baudrate to int 2012-10-19 15:25:44 -07:00
blackfin blackfin: Change global data baudrate to int 2012-10-19 15:25:45 -07:00
m68k m68k: Change bi_baudrate and global data baudrate to int 2012-10-19 15:25:44 -07:00
microblaze microblaze: Change bi_baudrate and global data baudrate to int 2012-10-19 15:25:44 -07:00
mips mips: Change global data baudrate to int 2012-10-19 15:25:45 -07:00
nds32 nds32: Change global data baudrate to int 2012-10-19 15:25:46 -07:00
nios2 nios2: Change bi_baudrate and global data baudrate to int 2012-10-19 15:25:44 -07:00
openrisc openrisc: Change bi_baudrate and global data baudrate to int 2012-10-19 15:25:45 -07:00
powerpc powerpc/corenet2: fix mismatch DDR sync bit from RCW 2012-10-22 14:31:20 -05:00
sandbox sandbox: Change global data baudrate to int 2012-10-19 15:25:46 -07:00
sh sh: Change bi_baudrate and global data baudrate to int 2012-10-19 15:25:44 -07:00
sparc sparc: Change bi_baudrate and global data baudrate to int 2012-10-19 15:25:45 -07:00
x86 x86: Change global data baudrate to int 2012-10-19 15:25:46 -07:00
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