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Stefan Roese a2c95a7224 PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance 
AMCC suggested to set the PMU bit to 0 for best performace on
the PPC440 DDR controller.
Please see doc/README.440-DDR-performance for details.
Patch by Stefan Roese, 28 Jul 2006
 		2006-07-28 18:34:58 +02:00
..
Makefile Update AMCC Yosemite to get a consistent setup for all AMCC eval 2005-09-15 11:34:07 +02:00
config.mk Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. 2005-08-01 16:41:48 +02:00
init.S Update AMCC Yosemite to get a consistent setup for all AMCC eval 2005-09-15 11:34:07 +02:00
u-boot.lds 2005-12-12 16:06:05 +01:00
yellowstone.c PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance 2006-07-28 18:34:58 +02:00