The cache of Cortex-A7 is only enabled if the SMP bit is set, but the SMP bit of V3s is wrongly left unset, because I thought that it's not SMP-capable. Fix this. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> |
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.. | ||
Makefile | ||
board.c | ||
clock.c | ||
clock_sun4i.c | ||
clock_sun6i.c | ||
clock_sun8i_a83t.c | ||
clock_sun9i.c | ||
cpu_info.c | ||
dram_helpers.c | ||
dram_sun4i.c | ||
dram_sun6i.c | ||
dram_sun8i_a23.c | ||
dram_sun8i_a33.c | ||
dram_sun8i_a83t.c | ||
dram_sun8i_h3.c | ||
dram_sun9i.c | ||
gtbus_sun9i.c | ||
p2wi.c | ||
pinmux.c | ||
pmic_bus.c | ||
prcm.c | ||
rsb.c | ||
usb_phy.c |