Prabhakar Kushwaha e87dc41fc1 powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting ... During NAND_SPL boot, base address and different register are programmed default by corresponding NAND controllers(eLBC/IFC). These settings are sufficient enough for NAND SPL. Avoid updating these register.They will be programmed during NAND RAMBOOT. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>		2012-07-06 17:30:31 -05:00
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cpu	powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting	2012-07-06 17:30:31 -05:00
include/asm	powerpc/mpc85xx:Add debugger support for e500v2 SoC	2012-07-06 17:30:31 -05:00
lib	net: move bootfile init into eth_initialize	2012-05-15 17:32:33 -05:00
config.mk	Handle most LDSCRIPT setting centrally	2011-04-30 00:59:47 +02:00