Michal Simek 7ba69b7dcc arm: zynq: Fix timer loadaddress ... Reload address was written to the counter register instead of load register. The problem happens when timer expires but never reload to ~0UL (it is downcount timer). Reported-by: Stephen MacMahon <stephenm@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>		2013-09-23 16:26:32 +02:00
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Makefile	zynq: Add new ddrc driver for ECC support	2013-08-12 08:59:55 +02:00
cpu.c	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
ddrc.c	zynq: Add new ddrc driver for ECC support	2013-08-12 08:59:55 +02:00
slcr.c	zynq: slcr: Wait 100ms till clk is properly setup	2013-08-12 08:59:55 +02:00
timer.c	arm: zynq: Fix timer loadaddress	2013-09-23 16:26:32 +02:00