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Poonam Aggrwal 66c74fca18 powerpc/85xx: Optimized DDR settings for 800MT/s on P1/P2 RDB 
Changed the following DDR timing parameters for 800Mt/s:
tRRT    BL/2+1 to  BL/2
tWWT    BL/2+1 to  BL/2
tWRT    BL/2+1 to  BL/2
tRWT    BL/2+1 to  BL/2
REFINT  6500ns to  7800ns

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
 		2011-04-04 09:24:42 -05:00
..
Makefile Switch from archive libraries to partial linking 2010-11-17 21:02:18 +01:00
ddr.c powerpc/85xx: Optimized DDR settings for 800MT/s on P1/P2 RDB 2011-04-04 09:24:42 -05:00
law.c powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe code 2011-01-14 01:32:20 -06:00
p1_p2_rdb.c powerpc/85xx: Removed P1/P2 RDB RevB support 2011-04-04 09:24:42 -05:00
pci.c powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe code 2011-01-14 01:32:20 -06:00
tlb.c powerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdb 2011-04-04 09:24:42 -05:00