Rajeshwari Shinde 6071bcaec1 EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 ... MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>		2012-09-01 14:58:23 +02:00
..
arm720t	ARM: add tegra20 support to arm720t	2012-09-01 14:58:22 +02:00
arm920t	…
arm925t	…
arm926ejs	…
arm946es	…
arm1136	…
arm1176	ARM: add basic support for the Broadcom BCM2835 SoC	2012-09-01 14:58:21 +02:00
arm_intcm	…
armv7	EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0	2012-09-01 14:58:23 +02:00
ixp	…
lh7a40x	…
pxa	…
s3c44b0	…
sa1100	…
tegra20-common	tegra20: Remove armv4t build flags	2012-09-01 14:58:22 +02:00
u-boot.lds	…