355f4f85e9
Now that we track which TLB CAM entries are used we can allocate entries on the fly. Change the SPD DDR TLB setup code to assume we use at most 8 TLBs (or the number free, which ever is fewer). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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| .. | ||
| Makefile | ||
| commproc.c | ||
| config.mk | ||
| cpu.c | ||
| cpu_init.c | ||
| cpu_init_early.c | ||
| cpu_init_nand.c | ||
| ddr-gen1.c | ||
| ddr-gen2.c | ||
| ddr-gen3.c | ||
| ether_fcc.c | ||
| fdt.c | ||
| fixed_ivor.S | ||
| interrupts.c | ||
| mp.c | ||
| mp.h | ||
| mpc8536_serdes.c | ||
| pci.c | ||
| qe_io.c | ||
| release.S | ||
| resetvec.S | ||
| serial_scc.c | ||
| speed.c | ||
| start.S | ||
| tlb.c | ||
| traps.c | ||
| u-boot-nand.lds | ||
| u-boot-nand_spl.lds | ||
| u-boot.lds | ||