Marek Vasut 0780697787 arm: socfpga: Actually enable L2 cache ... The L2 cache was never enabled in the v7_outer_cache_enable(), fix this and enable the L2 cache. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>		2015-12-22 04:42:27 +01:00
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arc	axs10x: add support of generic EHCI USB 2.0 controller	2015-12-08 17:29:56 +03:00
arm	arm: socfpga: Actually enable L2 cache	2015-12-22 04:42:27 +01:00
avr32	…
blackfin	…
m68k	m68k: add private libgcc	2015-12-13 20:22:00 -05:00
microblaze	microblaze: Enable DM by default	2015-12-18 13:15:58 +01:00
mips	…
nds32	…
nios2	nios2: display altera sysid at startup	2015-12-19 09:51:19 +08:00
openrisc	…
powerpc	fsl_*_serdes.c: Modify memset call in serdes_init	2015-12-13 18:27:29 -08:00
sandbox	timer: sandbox: Use device tree to pass the clock frequency	2015-12-01 06:23:51 -07:00
sh	…
sparc	sparc: Remove non-generic board init files: board.c, time.c	2015-12-03 13:15:50 +02:00
x86	x86: Remove HAVE_ACPI_RESUME	2015-12-09 17:44:56 +08:00
.gitignore	…
Kconfig	m68k: add private libgcc	2015-12-13 20:22:00 -05:00