467a40dfe3
Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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|---|---|---|
| .. | ||
| p_corenet | ||
| Makefile | ||
| arm_sleep.c | ||
| cadmus.c | ||
| cadmus.h | ||
| cds_pci_ft.c | ||
| cds_via.c | ||
| cmd_esbc_validate.c | ||
| dcu_sii9022a.c | ||
| dcu_sii9022a.h | ||
| diu_ch7301.c | ||
| diu_ch7301.h | ||
| eeprom.h | ||
| fman.c | ||
| fman.h | ||
| fsl_validate.c | ||
| ics307_clk.c | ||
| ics307_clk.h | ||
| idt8t49n222a_serdes_clk.c | ||
| idt8t49n222a_serdes_clk.h | ||
| ls102xa_stream_id.c | ||
| mpc85xx_sleep.c | ||
| ngpixis.c | ||
| ngpixis.h | ||
| ns_access.c | ||
| pfuze.c | ||
| pfuze.h | ||
| pixis.c | ||
| pixis.h | ||
| pq-mds-pib.c | ||
| pq-mds-pib.h | ||
| qixis.c | ||
| qixis.h | ||
| sdhc_boot.c | ||
| sgmii_riser.c | ||
| sgmii_riser.h | ||
| sleep.h | ||
| sys_eeprom.c | ||
| via.h | ||
| vid.c | ||
| vid.h | ||
| vsc3316_3308.c | ||
| vsc3316_3308.h | ||
| zm7300.c | ||
| zm7300.h | ||