Shaohui Xie abc7d0f75c armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY ... To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins polarity by setting IRQCR register, because AQR405 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>		2016-03-21 12:42:10 -07:00
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clock.h	…
config.h	armv8: lsch3: Enable WUO config for RNI-20 node	2016-03-21 12:42:10 -07:00
cpu.h	arm64: Remove non-full-va map code	2016-03-15 15:13:10 -04:00
fdt.h	armv8/ls1043aqds: add LS1043AQDS board support	2015-11-30 09:11:10 -08:00
fsl_serdes.h	armv8: ls2085a: Add support of LS2085A SoC	2015-11-30 09:10:47 -08:00
immap_lsch2.h	secure_boot: create function to determine boot mode	2016-01-27 08:12:42 -08:00
immap_lsch3.h	armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY	2016-03-21 12:42:10 -07:00
imx-regs.h	…
ls2080a_stream_id.h	armv8: LS2080A: Rename LS2085A to reflect LS2080A	2015-11-30 08:53:04 -08:00
mmu.h	…
mp.h	…
ns_access.h	…
soc.h	armv8: ls2040a: Add support of LS2040A SoC	2016-01-25 08:24:17 -08:00
speed.h	…