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Simon Glass 2b6051541b x86: ivybridge: Add early LPC init so that serial works 
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.

Signed-off-by: Simon Glass <sjg@chromium.org>
 		2014-11-21 07:34:12 +01:00
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Kconfig
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Makefile x86: ivybridge: Add early LPC init so that serial works 2014-11-21 07:34:12 +01:00
car.S x86: chromebook_link: Implement CAR support (cache as RAM) 2014-11-21 07:34:11 +01:00
cpu.c x86: ivybridge: Add early LPC init so that serial works 2014-11-21 07:34:12 +01:00
lpc.c x86: ivybridge: Add early LPC init so that serial works 2014-11-21 07:34:12 +01:00
pci.c x86: ivybridge: Enable PCI in early init 2014-11-21 07:34:12 +01:00
sdram.c
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