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Chin Liang See 89a54abf1b ddr: altera: Configuring SDRAM extra cycles timing parameters 
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
 		2016-10-27 08:03:07 +02:00
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arm ddr: altera: Configuring SDRAM extra cycles timing parameters 2016-10-27 08:03:07 +02:00
avr32 efi: Use asmlinkage for EFIAPI 2016-10-19 09:01:53 +02:00
blackfin common/Kconfig: Add DISPLAY_CPUINFO 2016-10-12 08:04:34 -04:00
m68k efi: Use asmlinkage for EFIAPI 2016-10-19 09:01:53 +02:00
microblaze efi: Use asmlinkage for EFIAPI 2016-10-19 09:01:53 +02:00
mips efi: Use asmlinkage for EFIAPI 2016-10-19 09:01:53 +02:00
nds32
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nios2 efi: Use asmlinkage for EFIAPI 2016-10-19 09:01:53 +02:00
openrisc efi: Use asmlinkage for EFIAPI 2016-10-19 09:01:53 +02:00
powerpc arch: powerpc: Remove unused dts frequency fixup for lbc_clk 2016-10-14 10:23:11 -07:00
sandbox efi: Use asmlinkage for EFIAPI 2016-10-19 09:01:53 +02:00
sh efi: Use asmlinkage for EFIAPI 2016-10-19 09:01:53 +02:00
sparc efi: Use asmlinkage for EFIAPI 2016-10-19 09:01:53 +02:00
x86 Patch queue for efi - 2016-10-19 2016-10-19 07:48:16 -04:00
xtensa
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.gitignore
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Kconfig
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