c63e137014
JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com> |
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| .. | ||
| Makefile | ||
| corenet_ds.c | ||
| corenet_ds.h | ||
| ddr.c | ||
| eth_hydra.c | ||
| eth_p4080.c | ||
| eth_superhydra.c | ||
| p3041ds_ddr.c | ||
| p4080ds_ddr.c | ||
| p5020ds_ddr.c | ||
| p5040ds_ddr.c | ||
| pbi.cfg | ||
| rcw_p2041rdb.cfg | ||
| rcw_p3041ds.cfg | ||
| rcw_p4080ds.cfg | ||
| rcw_p5020ds.cfg | ||
| rcw_p5040ds.cfg | ||