Priyanka Jain 0c871e952e powerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdb ... Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash boot loaders because: - P1_P2_RDB boards have soldered DDR so no need for SPD - Also P102x has 256K L2 cache size so becomes a limiting factor for size of image that could be loaded in SRAM mode and would require three stage boot loader (TPL). Changes done: 1. CONFIG_SYS_TEXT_BASE to 0x11000000 2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2011-04-04 09:24:42 -05:00
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Makefile	Switch from archive libraries to partial linking	2010-11-17 21:02:18 +01:00
ddr.c	powerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdb	2011-04-04 09:24:42 -05:00
law.c	powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe code	2011-01-14 01:32:20 -06:00
p1_p2_rdb.c	powerpc: Move cpu specific lmb reserve to arch_lmb_reserve	2011-04-04 09:24:40 -05:00
pci.c	powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe code	2011-01-14 01:32:20 -06:00
tlb.c	powerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdb	2011-04-04 09:24:42 -05:00