639200f6a0
Ensure that cache operations complete before returning from mips_cache_reset by placing a completion barrier (sync instruction) before the return. Without this there is no guarantee that the cache ops will complete before any subsequent memory accesses, since they are indexed cache ops & thus not implicitly ordered with memory accesses. Signed-off-by: Paul Burton <paul.burton@imgtec.com> |
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| .. | ||
| Makefile | ||
| ashldi3.c | ||
| ashrdi3.c | ||
| bootm.c | ||
| cache.c | ||
| cache_init.S | ||
| libgcc.h | ||
| lshrdi3.c | ||