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Author SHA1 Message Date
Masahiro Yamada 295326231d ARM: uniphier: enable SSC for more PLLs for LD20 SoC 
For Electro-Magnetic Compatibility.

Set CPLL, SPLL2, MPLL, VPPLL, GPPLL, DPLL* to SSC rate 1 percent.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
 2016-10-29 17:01:40 +09:00
Masahiro Yamada 682e09ff9f ARM: uniphier: add PLL init code for LD20 SoC 
Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot
proper.  Split the common code into pll-base-ld20.c for easier
re-use.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
 2016-09-19 00:12:26 +09:00