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5 Commits

Author SHA1 Message Date
Simon Glass dae594f210 rockchip: spl: Support full-speed CPU in SPL 
Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).

Signed-off-by: Simon Glass <sjg@chromium.org>
 2016-01-21 20:42:37 -07:00
Simon Glass 2460d18c33 rockchip: sdram: Use syscon_get_first_range() where possible 
This is a shortcut to obtaining a register address. Use it where possible, to
simplify the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
 2016-01-21 20:42:37 -07:00
Simon Glass 9368104d2f rockchip: sdram: Tidy up a few comments 
Fix spaces in two comments in this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
 2016-01-21 20:42:37 -07:00
Simon Glass 0906995bf3 rockchip: sdram: Use the rk_clr/setreg() interface 
Use this function in preference to the macro.

Signed-off-by: Simon Glass <sjg@chromium.org>
 2016-01-21 20:42:35 -07:00
Simon Glass 5ff093ab9e rockchip: rk3288: Add SDRAM init 
Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses
device tree for configuration so should be able to support other RAM
configurations. It may be possible to generalise the code to support other
SoCs at some point.

Signed-off-by: Simon Glass <sjg@chromium.org>
 2015-09-02 21:28:24 -06:00