ARC HS and ARC EM are new cores based on ARCv2 ISA which is binary
incompatible with ISAv1 (AKA ARCompact).
Significant difference between ISAv2 and v1 is implementation of
interrupt vector table.
In v1 it is implemented in the same way as on many other architectures -
as a special location where user may put whether code executed in place
(if machine word of space is enough) or jump to a full-scale interrupt
handler.
In v2 interrupt table is just an array of adresses of real interrupt
handlers. That requires a separate section for IVT that is not encoded
as code by assembler.
This change adds support for following cores:
* ARC EM6 (simple 32-bit microcontroller without MMU)
* ARC HS36 (advanced 32-bit microcontroller without MMU)
* ARC HS38 (advanced 32-bit microcontroller with MMU)
As a part of ARC HS38 new version of MMU (v4) was introduced.
Also this change adds AXS131 board which is the same DW ARC SDP base board but
with ARC HS38 CPU tile.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
r8a7794 uses ARM SoC of CA7 base. If we want to use dcache on CA7, we
need to enable SMP bit of Auxiliary Control Register.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
SILK is an entry level development board based on R-Car E2 SoC (R8A7794)
This commit supports the following peripherals:
- SCIF, I2C, Ethernet, QSPI, MMC, USB Host
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Reviewed-by: Tom Rini <trini@ti.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
With driver model the number of PIO ports is defined by platform data, so
remove it from the header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
These additional nodes need to be provided to get U-Boot to boot correctly
on the Canyonlands / Glacier board:
- chosen path to the console-uart
- reg-shift set to 0 in the uart device nodes
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Define an _end symbol indicating the end of u-boot.bin. Also add some dummy
words into the link script to ensure that u-boot.bin will always extend
that far. There may be a better way of doing this.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is required at present for device tree control. The ppc4xx does support
GPIOs but does not seem to have a proper driver. So this file is empty.
Signed-off-by: Simon Glass <sjg@chromium.org>
The canyonlands.h config file works with canyonlands, glacier and arches
boards. Bring in the device tree files for these from Linux 3.17.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a new ramboot config for glacier so that it is possible to test U-Boot
loaded over Ethernet instead of using JTAG.
Signed-off-by: Simon Glass <sjg@chromium.org>
Many CONFIG options have an unnecessary value of 1. CONFIG_440 is set in
the various board config files. Also simplify the CONFIG_440 check in
config.mk
Signed-off-by: Simon Glass <sjg@chromium.org>
When booting in JTAG mode, there is no way to use soft break-points, and
no way of knowing when SPL has finished executing (so the user can issue
a 'halt' command to load u-boot.bin for example)
Add a debug output and simple loop to stop execution at the completion of
the SPL initialisation as a pseudo break-point when booting in JTAG mode
Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
Section 4.1.2 of Freescale Application Note AN4199 describes the
configuration required to operate the mx28 from a 5V source without a
battery.
This patch changes the behaviour of the dropout control of the DC-DC
converter (refer to section 11.12.9 of the mx28 Application Processor
Reference Manual - Document Number: MCIMX28RM, Rev 2, 08/2013) to the
following:
- Always use 4P2 Linear Regulator if CONFIG_SYS_MXS_VDD5V_ONLY is defined
- Switch between 4P2 Linear Regulator and Battery, using whichever has
the highest voltage if CONFIG_SYS_MXS_VDD5V_ONLY isnot set (this is
the same as the pre-patch behaviour)
Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
Signed-off-by: Damien Gotfroi <dgotfroi@greenwatch.be>
It is difficult to track down fail to boot issues in the mxs SPL.
Implement the following to make it easier:
- Add debug outputs to allow tracing of SPL progress in order to track
where failure to boot occurs. DEUBUG and CONFIG_SPL_SERIAL_SUPPORT must
be defined to enable debug output in SPL
- Add TODO comments where it is not clear if the code is doing what it
is meant to be doing, even tough the board boots properly (these comments
refer to existing code, not to any code added by this patch)
Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
Should use AIPS3 configuration address 0x0227C000 to set AIPS3,
not the AIPS3 base address.
Additional, replace AIPS1_BASE_ADDR to AIPS3_ARB_BASE_ADDR to align with
AIPS1 and AIPS2, and resolve the AIPS3_ARB_BASE_ADDR undefine problem.
Signed-off-by: Ye.Li <B37916@freescale.com>
This patch has some parts connected together:
- Use _gd in bss section which is automatically cleared
Location at SPL_MALLOC_END wasn't cleared at all
- Use MALLOC_F_LEN(early alloc) instead of FULL MALLOC
(mem_malloc_init is not called at all)
- Simplify malloc and stack init.
At the end of SPL addr is malloc area and below is stack
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Because it is not compatible with DM where
malloc_base has to be available early and init
has to be done in ASM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Compile code with -fPIC to get GOT. Do not build SPL
with fPIC because it increasing SPL size for nothing.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Setup gd from ASM to be availalbe for board_init_r.
Setting it up in spl_board_init is too late when
MALLOC is used.
Space for gd is located behind MALLOC area at the end of BRAM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Do not use specific macros for debugging.
Also remove compilation warning:
w+../arch/microblaze/cpu/interrupts.c: In function 'interrupt_handler':
w+../arch/microblaze/cpu/interrupts.c:153:2: warning: format '%x'
expects argument of type 'unsigned int', but argument 2 has type 'void
(*)(void *)' [-Wformat]
w+../arch/microblaze/cpu/interrupts.c:153:2: warning: format '%x'
expects argument of type 'unsigned int', but argument 4 has type 'void
*' [-Wformat]
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tom Rini
Alexey Brodkin
Nobuhiro Iwamatsu
Vladimir Barinov
Simon Glass
Stefan Roese
Graeme Russ
Ye.Li
Peng Fan
Michal Simek