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General indent and whitespace cleanups.

This commit is contained in:
Jon Loeliger 2006-08-22 12:06:18 -05:00
parent 41a0e8b304
commit ffff3ae56f
9 changed files with 331 additions and 352 deletions
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24
cpu/mpc86xx/cpu.c
View File

@ -38,7 +38,8 @@ extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag,
#endif
int checkcpu (void)
int
checkcpu(void)
{
sys_info_t sysinfo;
uint pvr, svr;
@ -126,8 +127,10 @@ soft_restart(unsigned long addr)
{
#ifndef CONFIG_MPC8641HPCN
/* SRR0 has system reset vector, SRR1 has default MSR value */
/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
/*
* SRR0 has system reset vector, SRR1 has default MSR value
* rfi restores MSR from SRR1 and sets the PC to the SRR0 value
*/
__asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
__asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
@ -192,7 +195,8 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/*
* Get timebase clock frequency
*/
unsigned long get_tbclk(void)
unsigned long
get_tbclk(void)
{
sys_info_t sys_info;
@ -210,7 +214,8 @@ watchdog_reset(void)
#if defined(CONFIG_DDR_ECC)
void dma_init(void)
void
dma_init(void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
@ -220,7 +225,8 @@ void dma_init(void)
asm("sync; isync");
}
uint dma_check(void)
uint
dma_check(void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
@ -237,7 +243,8 @@ uint dma_check(void)
return status;
}
int dma_xfer(void *dest, uint count, void *src)
int
dma_xfer(void *dest, uint count, void *src)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
@ -256,7 +263,8 @@ int dma_xfer(void *dest, uint count, void *src)
#ifdef CONFIG_OF_FLAT_TREE
void ft_cpu_setup(void *blob, bd_t *bd)
void
ft_cpu_setup(void *blob, bd_t *bd)
{
u32 *p;
ulong clock;

12
cpu/mpc86xx/i2c.c
View File

@ -174,8 +174,7 @@ __i2c_read (u8 *data, int length)
/* Generate ack on last next to last byte */
if (i == length - 2)
writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA
| MPC86xx_I2CCR_TXAK,
I2CCCR);
| MPC86xx_I2CCR_TXAK, I2CCCR);
/* Generate stop on last byte */
if (i == length - 1)
@ -236,7 +235,8 @@ exit:
return !(i == length);
}
int i2c_probe (uchar chip)
int
i2c_probe(uchar chip)
{
int tmp;
@ -250,7 +250,8 @@ int i2c_probe (uchar chip)
return i2c_read(chip, 0, 1, (char *)&tmp, 1);
}
uchar i2c_reg_read (uchar i2c_addr, uchar reg)
uchar
i2c_reg_read(uchar i2c_addr, uchar reg)
{
char buf[1];
@ -259,7 +260,8 @@ uchar i2c_reg_read (uchar i2c_addr, uchar reg)
return buf[0];
}
void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
void
i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
{
i2c_write(i2c_addr, reg, 1, &val, 1);
}

36
cpu/mpc86xx/interrupts.c
View File

@ -64,7 +64,6 @@ static __inline__ unsigned long get_dec (void)
return val;
}
static __inline__ void set_dec(unsigned long val)
{
if (val)
@ -77,7 +76,6 @@ int interrupt_init_cpu (unsigned *decrementer_count)
return 0;
}
int interrupt_init(void)
{
int ret;
@ -89,18 +87,21 @@ int interrupt_init (void)
return ret;
decrementer_count = get_tbclk() / CFG_HZ;
debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", (get_tbclk()/1000000), decrementer_count);
debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n",
(get_tbclk() / 1000000),
decrementer_count);
set_dec(decrementer_count);
set_msr(get_msr() | MSR_EE);
debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec());
debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n",
get_msr(),
get_dec());
return 0;
}
void enable_interrupts(void)
{
set_msr(get_msr() | MSR_EE);
@ -115,7 +116,6 @@ int disable_interrupts (void)
return (msr & MSR_EE) != 0;
}
void increment_timestamp(void)
{
timestamp++;
@ -126,13 +126,11 @@ void increment_timestamp(void)
* with interrupts disabled.
* Trivial implementation - no need to be really accurate.
*/
void
timer_interrupt_cpu (struct pt_regs *regs)
void timer_interrupt_cpu(struct pt_regs *regs)
{
/* nothing to do here */
}
void timer_interrupt(struct pt_regs *regs)
{
/* call cpu specific function from $(CPU)/interrupts.c */
@ -158,7 +156,6 @@ void timer_interrupt (struct pt_regs *regs)
board_show_activity(timestamp);
#endif /* CONFIG_SHOW_ACTIVITY */
}
void reset_timer(void)
@ -180,22 +177,18 @@ void set_timer (ulong t)
* Install and free a interrupt handler. Not implemented yet.
*/
void
irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
{
}
void
irq_free_handler(int vec)
void irq_free_handler(int vec)
{
}
/*
* irqinfo - print information about PCI devices,not implemented.
*/
int
do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
printf("\nInterrupt-unsupported:\n");
@ -205,14 +198,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/*
* Handle external interrupts
*/
void
external_interrupt(struct pt_regs *regs)
void external_interrupt(struct pt_regs *regs)
{
puts("external_interrupt (oops!)\n");
}

35
cpu/mpc86xx/pci.c
View File

@ -47,46 +47,53 @@ pci_mpc86xx_init(struct pci_controller *hose)
uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 ||
io_sel == 7 || io_sel == 0xf) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
io_sel == 7 || io_sel == 0xf)
&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
printf("PCI-EXPRESS 1: Configured as %s \n",
pcie1_agent ? "Agent" : "Host");
if(pcie1_agent) return; /*Don't scan bus when configured as agent*/
if (pcie1_agent)
return; /*Don't scan bus when configured as agent */
printf(" Scanning PCIE bus");
debug("0x%08x=0x%08x ", &pcie1->pme_msg_det,pcie1->pme_msg_det);
debug("0x%08x=0x%08x ",
&pcie1->pme_msg_det,
pcie1->pme_msg_det);
if (pcie1->pme_msg_det) {
pcie1->pme_msg_det = 0xffffffff;
debug(" with errors. Clearing. Now 0x%08x",
pcie1->pme_msg_det);
}
debug("\n");
}
else{
} else {
printf("PCI-EXPRESS 1 disabled!\n");
return;
}
/*set first_bus=0 only skipped B0:D0:F0 which is
/*
* Set first_bus=0 only skipped B0:D0:F0 which is
* a reserved device in M1575, but make it easy for
* most of the scan process.
*/
hose->first_busno = 0x00;
hose->last_busno = 0xfe;
pcie_setup_indirect(hose,
(CFG_IMMR+0x8000),
(CFG_IMMR+0x8004));
pcie_setup_indirect(hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004));
pci_hose_read_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, &temp16);
pci_hose_read_config_word(hose,
PCI_BDF(0, 0, 0), PCI_COMMAND, &temp16);
temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, temp16);
pci_hose_write_config_word(hose,
PCI_BDF(0, 0, 0), PCI_COMMAND, temp16);
pci_hose_write_config_word(hose, PCI_BDF(0, 0, 0), PCI_STATUS, 0xffff);
pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, 0x80);
pci_hose_write_config_byte(hose,
PCI_BDF(0, 0, 0), PCI_LATENCY_TIMER, 0x80);
pci_hose_read_config_dword(hose, PCI_BDF(0,0,0), PCI_PRIMARY_BUS, &temp32);
pci_hose_read_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS,
&temp32);
temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16);
pci_hose_write_config_dword(hose, PCI_BDF(0,0,0), PCI_PRIMARY_BUS, temp32);
pci_hose_write_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS,
temp32);
pcie1->powar1 = 0;
pcie1->powar2 = 0;

22
cpu/mpc86xx/pcie_indirect.c
View File

@ -28,8 +28,10 @@
static int
indirect_read_config_pcie(struct pci_controller *hose,
pci_dev_t dev, int offset,
int len,u32 *val)
pci_dev_t dev,
int offset,
int len,
u32 *val)
{
int bus = PCI_BUS(dev);
@ -38,9 +40,11 @@ indirect_read_config_pcie(struct pci_controller *hose,
PEX_FIX;
if (bus == 0xff) {
PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001);
PCI_CFG_OUT(hose->cfg_addr,
dev | (offset & 0xfc) | 0x80000001);
} else {
PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);
PCI_CFG_OUT(hose->cfg_addr,
dev | (offset & 0xfc) | 0x80000000);
}
/*
* Note: the caller has already checked that offset is
@ -78,9 +82,11 @@ indirect_write_config_pcie(struct pci_controller *hose,
PEX_FIX;
if (bus == 0xff) {
PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001);
PCI_CFG_OUT(hose->cfg_addr,
dev | (offset & 0xfc) | 0x80000001);
} else {
PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);
PCI_CFG_OUT(hose->cfg_addr,
dev | (offset & 0xfc) | 0x80000000);
}
/*
@ -176,9 +182,7 @@ indirect_write_config_dword_pcie(struct pci_controller *hose,
}
void
pcie_setup_indirect(struct pci_controller* hose,
u32 cfg_addr,
u32 cfg_data)
pcie_setup_indirect(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
{
pci_set_ops(hose,
indirect_read_config_byte_pcie,

123
cpu/mpc86xx/start.S
View File

@ -662,142 +662,140 @@ get_svr:
blr
/*------------------------------------------------------------------------------- */
/* Function: in8 */
/* Description: Input 8 bits */
/*------------------------------------------------------------------------------- */
/*
* Function: in8
* Description: Input 8 bits
*/
.globl in8
in8:
lbz r3,0x0000(r3)
blr
/*------------------------------------------------------------------------------- */
/* Function: out8 */
/* Description: Output 8 bits */
/*------------------------------------------------------------------------------- */
/*
* Function: out8
* Description: Output 8 bits
*/
.globl out8
out8:
stb r4,0x0000(r3)
blr
/*------------------------------------------------------------------------------- */
/* Function: out16 */
/* Description: Output 16 bits */
/*------------------------------------------------------------------------------- */
/*
* Function: out16
* Description: Output 16 bits
*/
.globl out16
out16:
sth r4,0x0000(r3)
blr
/*------------------------------------------------------------------------------- */
/* Function: out16r */
/* Description: Byte reverse and output 16 bits */
/*------------------------------------------------------------------------------- */
/*
* Function: out16r
* Description: Byte reverse and output 16 bits
*/
.globl out16r
out16r:
sthbrx r4,r0,r3
blr
/*------------------------------------------------------------------------------- */
/* Function: out32 */
/* Description: Output 32 bits */
/*------------------------------------------------------------------------------- */
/*
* Function: out32
* Description: Output 32 bits
*/
.globl out32
out32:
stw r4,0x0000(r3)
blr
/*------------------------------------------------------------------------------- */
/* Function: out32r */
/* Description: Byte reverse and output 32 bits */
/*------------------------------------------------------------------------------- */
/*
* Function: out32r
* Description: Byte reverse and output 32 bits
*/
.globl out32r
out32r:
stwbrx r4,r0,r3
blr
/*------------------------------------------------------------------------------- */
/* Function: in16 */
/* Description: Input 16 bits */
/*------------------------------------------------------------------------------- */
/*
* Function: in16
* Description: Input 16 bits
*/
.globl in16
in16:
lhz r3,0x0000(r3)
blr
/*------------------------------------------------------------------------------- */
/* Function: in16r */
/* Description: Input 16 bits and byte reverse */
/*------------------------------------------------------------------------------- */
/*
* Function: in16r
* Description: Input 16 bits and byte reverse
*/
.globl in16r
in16r:
lhbrx r3,r0,r3
blr
/*------------------------------------------------------------------------------- */
/* Function: in32 */
/* Description: Input 32 bits */
/*------------------------------------------------------------------------------- */
/*
* Function: in32
* Description: Input 32 bits
*/
.globl in32
in32:
lwz 3,0x0000(3)
blr
/*------------------------------------------------------------------------------- */
/* Function: in32r */
/* Description: Input 32 bits and byte reverse */
/*------------------------------------------------------------------------------- */
/*
* Function: in32r
* Description: Input 32 bits and byte reverse
*/
.globl in32r
in32r:
lwbrx r3,r0,r3
blr
/*------------------------------------------------------------------------------- */
/* Function: ppcDcbf */
/* Description: Data Cache block flush */
/* Input: r3 = effective address */
/* Output: none. */
/*------------------------------------------------------------------------------- */
/*
* Function: ppcDcbf
* Description: Data Cache block flush
* Input: r3 = effective address
* Output: none.
*/
.globl ppcDcbf
ppcDcbf:
dcbf r0,r3
blr
/*------------------------------------------------------------------------------- */
/* Function: ppcDcbi */
/* Description: Data Cache block Invalidate */
/* Input: r3 = effective address */
/* Output: none. */
/*------------------------------------------------------------------------------- */
/*
* Function: ppcDcbi
* Description: Data Cache block Invalidate
* Input: r3 = effective address
* Output: none.
*/
.globl ppcDcbi
ppcDcbi:
dcbi r0,r3
blr
/*--------------------------------------------------------------------------
/*
* Function: ppcDcbz
* Description: Data Cache block zero.
* Input: r3 = effective address
* Output: none.
*-------------------------------------------------------------------------- */
*/
.globl ppcDcbz
ppcDcbz:
dcbz r0,r3
blr
/*-------------------------------------------------------------------------- */
/* Function: ppcSync */
/* Description: Processor Synchronize */
/* Input: none. */
/* Output: none. */
/*-------------------------------------------------------------------------- */
/*
* Function: ppcSync
* Description: Processor Synchronize
* Input: none.
* Output: none.
*/
.globl ppcSync
ppcSync:
sync
blr
/*-----------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
@ -1205,7 +1203,6 @@ secondary_cpu_setup:
bl icache_enable
sync
/* TBEN in HID0 */
mfspr r4, HID0
oris r4, r4, 0x0400

47
cpu/mpc86xx/traps.c
View File

@ -64,7 +64,8 @@ print_backtrace(unsigned long *sp)
if (cnt++ % 7 == 0)
printf("\n");
printf("%08lX ", i);
if (cnt > 32) break;
if (cnt > 32)
break;
sp = (unsigned long *)*sp;
}
printf("\n");
@ -80,21 +81,19 @@ show_regs(struct pt_regs * regs)
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
printf("MSR: %08lx EE: %01x PR: %01x FP:"
" %01x ME: %01x IR/DR: %01x%01x\n",
regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
regs->msr&MSR_IR ? 1 : 0,
regs->msr, regs->msr & MSR_EE ? 1 : 0,
regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0,
regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0,
regs->msr & MSR_DR ? 1 : 0);
printf("\n");
for (i = 0; i < 32; i++) {
if ((i % 8) == 0)
{
if ((i % 8) == 0) {
printf("GPR%02d: ", i);
}
printf("%08lX ", regs->gpr[i]);
if ((i % 8) == 7)
{
if ((i % 8) == 7) {
printf("\n");
}
}
@ -203,7 +202,6 @@ SoftEmuException(struct pt_regs *regs)
panic("Software Emulation Exception");
}
void
UnknownException(struct pt_regs *regs)
{
@ -216,36 +214,13 @@ UnknownException(struct pt_regs *regs)
_exception(0, regs);
}
/* Probe an address by reading. If not present, return -1, otherwise
* return 0.
/*
* Probe an address by reading.
* If not present, return -1,
* otherwise return 0.
*/
int
addr_probe(uint *addr)
{
#if 0
int retval;
__asm__ __volatile__( \
"1: lwz %0,0(%1)\n" \
" eieio\n" \
" li %0,0\n" \
"2:\n" \
".section .fixup,\"ax\"\n" \
"3: li %0,-1\n" \
" b 2b\n" \
".section __ex_table,\"a\"\n" \
" .align 2\n" \
" .long 1b,3b\n" \
".text" \
: "=r" (retval) : "r"(addr));
return (retval);
#endif
return 0;
}