dm: i2c: Add driver for Cadence I2C IP
This is a possible drop in replacement for drivers/i2c/zynq-i2c.c Since this is cadence IP it has been renamed to cdns-i2c, to make sense with the compatible string. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Moritz Fischer
Michal Simek
parent
17573c2791
commit
fdec2d21ef
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@ -58,6 +58,13 @@ config DM_I2C_GPIO
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bindings are supported.
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Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
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config SYS_I2C_CADENCE
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tristate "Cadence I2C Controller"
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depends on DM_I2C && (ARCH_ZYNQ || ARM64)
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help
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Say yes here to select Cadence I2C Host Controller. This controller is
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e.g. used by Xilinx Zynq.
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config SYS_I2C_INTEL
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bool "Intel I2C/SMBUS driver"
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depends on DM_I2C
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@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
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obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
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obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
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obj-$(CONFIG_SYS_I2C) += i2c_core.o
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obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
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obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
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obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
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obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
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@ -0,0 +1,335 @@
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/*
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* Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
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* IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
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*
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* This file is based on: drivers/i2c/zynq_i2c.c,
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* with added driver-model support and code cleanup.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/types.h>
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#include <linux/io.h>
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#include <asm/errno.h>
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#include <dm/device.h>
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#include <dm/root.h>
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#include <i2c.h>
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#include <fdtdec.h>
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#include <mapmem.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* i2c register set */
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struct cdns_i2c_regs {
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u32 control;
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u32 status;
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u32 address;
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u32 data;
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u32 interrupt_status;
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u32 transfer_size;
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u32 slave_mon_pause;
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u32 time_out;
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u32 interrupt_mask;
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u32 interrupt_enable;
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u32 interrupt_disable;
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};
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/* Control register fields */
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#define CDNS_I2C_CONTROL_RW 0x00000001
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#define CDNS_I2C_CONTROL_MS 0x00000002
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#define CDNS_I2C_CONTROL_NEA 0x00000004
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#define CDNS_I2C_CONTROL_ACKEN 0x00000008
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#define CDNS_I2C_CONTROL_HOLD 0x00000010
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#define CDNS_I2C_CONTROL_SLVMON 0x00000020
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#define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040
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#define CDNS_I2C_CONTROL_DIV_B_SHIFT 8
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#define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00
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#define CDNS_I2C_CONTROL_DIV_A_SHIFT 14
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#define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000
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/* Status register values */
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#define CDNS_I2C_STATUS_RXDV 0x00000020
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#define CDNS_I2C_STATUS_TXDV 0x00000040
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#define CDNS_I2C_STATUS_RXOVF 0x00000080
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#define CDNS_I2C_STATUS_BA 0x00000100
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/* Interrupt register fields */
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#define CDNS_I2C_INTERRUPT_COMP 0x00000001
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#define CDNS_I2C_INTERRUPT_DATA 0x00000002
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#define CDNS_I2C_INTERRUPT_NACK 0x00000004
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#define CDNS_I2C_INTERRUPT_TO 0x00000008
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#define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010
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#define CDNS_I2C_INTERRUPT_RXOVF 0x00000020
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#define CDNS_I2C_INTERRUPT_TXOVF 0x00000040
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#define CDNS_I2C_INTERRUPT_RXUNF 0x00000080
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#define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200
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#define CDNS_I2C_FIFO_DEPTH 16
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#define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
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#ifdef DEBUG
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static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
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{
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int int_status;
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int status;
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int_status = readl(&cdns_i2c->interrupt_status);
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status = readl(&cdns_i2c->status);
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if (int_status || status) {
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debug("Status: ");
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if (int_status & CDNS_I2C_INTERRUPT_COMP)
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debug("COMP ");
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if (int_status & CDNS_I2C_INTERRUPT_DATA)
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debug("DATA ");
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if (int_status & CDNS_I2C_INTERRUPT_NACK)
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debug("NACK ");
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if (int_status & CDNS_I2C_INTERRUPT_TO)
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debug("TO ");
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if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
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debug("SLVRDY ");
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if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
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debug("RXOVF ");
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if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
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debug("TXOVF ");
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if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
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debug("RXUNF ");
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if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
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debug("ARBLOST ");
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if (status & CDNS_I2C_STATUS_RXDV)
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debug("RXDV ");
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if (status & CDNS_I2C_STATUS_TXDV)
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debug("TXDV ");
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if (status & CDNS_I2C_STATUS_RXOVF)
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debug("RXOVF ");
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if (status & CDNS_I2C_STATUS_BA)
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debug("BA ");
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debug("TS%d ", readl(&cdns_i2c->transfer_size));
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debug("\n");
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}
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}
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#endif
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struct i2c_cdns_bus {
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int id;
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struct cdns_i2c_regs __iomem *regs; /* register base */
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};
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/** cdns_i2c_probe() - Probe method
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* @dev: udevice pointer
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*
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* DM callback called when device is probed
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*/
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static int cdns_i2c_probe(struct udevice *dev)
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{
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struct i2c_cdns_bus *bus = dev_get_priv(dev);
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bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
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if (!bus->regs)
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return -ENOMEM;
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/* TODO: Calculate dividers based on CPU_CLK_1X */
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/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
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writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
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(2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
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/* Enable master mode, ack, and 7-bit addressing */
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setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
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CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
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debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
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return 0;
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}
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static int cdns_i2c_remove(struct udevice *dev)
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{
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struct i2c_cdns_bus *bus = dev_get_priv(dev);
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debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
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unmap_sysmem(bus->regs);
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return 0;
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}
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/* Wait for an interrupt */
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static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
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{
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int timeout, int_status;
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for (timeout = 0; timeout < 100; timeout++) {
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udelay(100);
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int_status = readl(&cdns_i2c->interrupt_status);
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if (int_status & mask)
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break;
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}
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/* Clear interrupt status flags */
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writel(int_status & mask, &cdns_i2c->interrupt_status);
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return int_status & mask;
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}
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static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
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{
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if (speed != 100000) {
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printf("%s, failed to set clock speed to %u\n", __func__,
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speed);
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return -EINVAL;
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}
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return 0;
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}
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/* Probe to see if a chip is present. */
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static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr,
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uint chip_flags)
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{
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struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus);
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struct cdns_i2c_regs *regs = i2c_bus->regs;
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/* Attempt to read a byte */
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setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
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CDNS_I2C_CONTROL_RW);
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clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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writel(0xFF, ®s->interrupt_status);
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writel(chip_addr, ®s->address);
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writel(1, ®s->transfer_size);
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return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
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CDNS_I2C_INTERRUPT_NACK) &
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CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
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}
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static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
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u32 len, bool next_is_read)
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{
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u8 *cur_data = data;
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struct cdns_i2c_regs *regs = i2c_bus->regs;
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setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
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CDNS_I2C_CONTROL_HOLD);
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/* if next is a read, we need to clear HOLD, doesn't work */
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if (next_is_read)
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clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW);
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writel(0xFF, ®s->interrupt_status);
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writel(addr, ®s->address);
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while (len--) {
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writel(*(cur_data++), ®s->data);
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if (readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
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if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) {
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/* Release the bus */
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clrbits_le32(®s->control,
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CDNS_I2C_CONTROL_HOLD);
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return -ETIMEDOUT;
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}
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}
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}
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/* All done... release the bus */
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clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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/* Wait for the address and data to be sent */
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if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
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return -ETIMEDOUT;
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return 0;
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}
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static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
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u32 len)
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{
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u32 status;
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u32 i = 0;
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u8 *cur_data = data;
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/* TODO: Fix this */
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struct cdns_i2c_regs *regs = i2c_bus->regs;
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/* Check the hardware can handle the requested bytes */
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if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX))
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return -EINVAL;
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setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
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CDNS_I2C_CONTROL_RW);
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/* Start reading data */
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writel(addr, ®s->address);
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writel(len, ®s->transfer_size);
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/* Wait for data */
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do {
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status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
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CDNS_I2C_INTERRUPT_DATA);
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if (!status) {
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/* Release the bus */
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clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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return -ETIMEDOUT;
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}
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debug("Read %d bytes\n",
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len - readl(®s->transfer_size));
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for (; i < len - readl(®s->transfer_size); i++)
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*(cur_data++) = readl(®s->data);
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} while (readl(®s->transfer_size) != 0);
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/* All done... release the bus */
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clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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#ifdef DEBUG
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cdns_i2c_debug_status(regs);
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#endif
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return 0;
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}
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static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
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int nmsgs)
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{
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struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
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int ret;
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debug("i2c_xfer: %d messages\n", nmsgs);
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for (; nmsgs > 0; nmsgs--, msg++) {
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bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
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debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
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if (msg->flags & I2C_M_RD) {
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ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
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msg->len);
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} else {
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ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
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msg->len, next_is_read);
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}
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if (ret) {
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debug("i2c_write: error sending\n");
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return -EREMOTEIO;
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}
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}
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return 0;
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}
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static const struct dm_i2c_ops cdns_i2c_ops = {
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.xfer = cdns_i2c_xfer,
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.probe_chip = cdns_i2c_probe_chip,
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.set_bus_speed = cdns_i2c_set_bus_speed,
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};
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static const struct udevice_id cdns_i2c_of_match[] = {
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{ .compatible = "cdns,i2c-r1p10" },
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{ /* end of table */ }
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};
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U_BOOT_DRIVER(cdns_i2c) = {
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.name = "i2c-cdns",
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.id = UCLASS_I2C,
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.of_match = cdns_i2c_of_match,
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.probe = cdns_i2c_probe,
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.remove = cdns_i2c_remove,
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.priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
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.ops = &cdns_i2c_ops,
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};
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