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net: fec: do not access reserved register for i.MX6UL 

The MIB RAM and FIFO receive start register does not exist on
i.MX6UL. Accessing these register will cause enet not work well.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan 2015-08-12 17:46:51 +08:00 committed by Stefano Babic
parent 6d97dc10a8
commit fbecbaa158
1 changed files with 9 additions and 5 deletions
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14
drivers/net/fec_mxc.c
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@ -17,6 +17,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/sys_proto.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <linux/compiler.h>
@ -551,12 +552,15 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
writel(0x00000000, &fec->eth->gaddr2);
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
/* Do not access reserved register for i.MX6UL */
if (!is_cpu_type(MXC_CPU_MX6UL)) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
/* FIFO receive start register */
writel(0x520, &fec->eth->r_fstart);
/* FIFO receive start register */
writel(0x520, &fec->eth->r_fstart);
}
/* size and address of each buffer */
writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);