arm64: mvebu: Add pin control nodes to A8K family DTS files
Add pin control nodes to APN806, CP-master, CP-slave and Armada-7040 and Armada-8040 boards DTS files Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Konstantin Porotchkin
Stefan Roese
parent
656e6cc86b
commit
f99386c5b1
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@ -66,6 +66,16 @@
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};
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};
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&ap_pinctl {
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/* MPP Bus:
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* SDIO [0-5]
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* UART0 [11,19]
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 1 1 1 1 1 1 0 0 0 0
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0 3 0 0 0 0 0 0 0 3 >;
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};
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&uart0 {
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status = "okay";
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};
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@ -76,11 +86,37 @@
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};
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&cpm_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_i2c0_pins>;
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status = "okay";
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clock-frequency = <100000>;
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};
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&cpm_pinctl {
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/* MPP Bus:
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* TDM [0-11]
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* SPI [13-16]
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* SATA1 [28]
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* UART0 [29-30]
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* SMI [32,34]
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* XSMI [35-36]
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* I2C [37-38]
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* RGMII1[44-55]
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* SD [56-62]
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 4 4 4 4 4 4 4 4 4 4
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4 4 0 3 3 3 3 0 0 0
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0 0 0 0 0 0 0 0 9 0xA
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0xA 0 7 0 7 7 7 2 2 0
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0 0 0 0 1 1 1 1 1 1
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1 1 1 1 1 1 0xE 0xE 0xE 0xE
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0xE 0xE 0xE >;
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};
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&cpm_spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_spi0_pins>;
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status = "okay";
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spi-flash@0 {
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@ -71,6 +71,41 @@
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status = "okay";
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};
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&ap_pinctl {
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/* MPP Bus:
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* SDIO [0-10]
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* UART0 [11,19]
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 1 1 1 1 1 1 1 1 1 1
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1 3 0 0 0 0 0 0 0 3 >;
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};
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&cpm_pinctl {
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/* MPP Bus:
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* [0-31] = 0xff: Keep default CP0_shared_pins:
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* [11] CLKOUT_MPP_11 (out)
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* [23] LINK_RD_IN_CP2CP (in)
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* [25] CLKOUT_MPP_25 (out)
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* [29] AVS_FB_IN_CP2CP (in)
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* [32,34] SMI
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* [31] GPIO: push button/Wake
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* [35-36] GPIO
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* [37-38] I2C
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* [40-41] SATA[0/1]_PRESENT_ACTIVEn
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* [42-43] XSMI
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* [44-55] RGMII1
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* [56-62] SD
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0 7 0 7 0 0 2 2 0
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0 0 8 8 1 1 1 1 1 1
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1 1 1 1 1 1 0xe 0xe 0xe 0xe
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0xe 0xe 0xe >;
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};
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/* CON5 on CP0 expansion */
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&cpm_pcie2 {
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@ -78,6 +113,8 @@
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};
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&cpm_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_i2c0_pins>;
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status = "okay";
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clock-frequency = <100000>;
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};
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@ -97,12 +134,31 @@
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status = "okay";
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};
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&cps_pinctl {
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/* MPP Bus:
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* [0-11] RGMII0
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* [13-16] SPI1
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* [27,31] GE_MDIO/MDC
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* [32-62] = 0xff: Keep default CP1_shared_pins:
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
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0x3 0x3 0xff 0x3 0x3 0x3 0x3 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0xff 0xff
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0xff 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff >;
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};
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/* CON5 on CP1 expansion */
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&cps_pcie2 {
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status = "okay";
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};
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&cps_spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cps_spi1_pins>;
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status = "okay";
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spi-flash@0 {
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@ -140,6 +140,24 @@
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marvell,spi-base = <128>, <136>, <144>, <152>;
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};
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ap_pinctl: ap-pinctl@6F4000 {
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compatible = "marvell,armada-ap806-pinctrl";
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bank-name ="apn-806";
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reg = <0x6F4000 0x10>;
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pin-count = <20>;
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max-func = <3>;
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ap_i2c0_pins: i2c-pins-0 {
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marvell,pins = < 4 5 >;
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marvell,function = <3>;
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};
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ap_emmc_pins: emmc-pins-0 {
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marvell,pins = < 0 1 2 3 4 5 6 7
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8 9 10 >;
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marvell,function = <1>;
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};
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};
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xor@400000 {
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compatible = "marvell,mv-xor-v2";
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reg = <0x400000 0x1000>,
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@ -81,6 +81,38 @@
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"cpm-usb3dev", "cpm-eip150", "cpm-eip197";
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};
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cpm_pinctl: cpm-pinctl@440000 {
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compatible = "marvell,mvebu-pinctrl",
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"marvell,a70x0-pinctrl",
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"marvell,a80x0-cp0-pinctrl";
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bank-name ="cp0-110";
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reg = <0x440000 0x20>;
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pin-count = <63>;
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max-func = <0xf>;
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cpm_i2c0_pins: cpm-i2c-pins-0 {
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marvell,pins = < 37 38 >;
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marvell,function = <2>;
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};
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cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 {
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marvell,pins = < 44 45 46 47 48 49 50 51
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52 53 54 55 >;
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marvell,function = <1>;
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};
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pca0_pins: cpm-pca0_pins {
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marvell,pins = <62>;
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marvell,function = <0>;
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};
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cpm_sdhci_pins: cpm-sdhi-pins-0 {
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marvell,pins = < 56 57 58 59 60 61 >;
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marvell,function = <14>;
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};
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cpm_spi0_pins: cpm-spi-pins-0 {
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marvell,pins = < 13 14 15 16 >;
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marvell,function = <3>;
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};
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};
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cpm_sata0: sata@540000 {
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compatible = "marvell,armada-8k-ahci";
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reg = <0x540000 0x30000>;
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@ -81,6 +81,25 @@
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"cps-usb3dev", "cps-eip150", "cps-eip197";
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};
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cps_pinctl: cps-pinctl@440000 {
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compatible = "marvell,mvebu-pinctrl",
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"marvell,a80x0-cp1-pinctrl";
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bank-name ="cp1-110";
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reg = <0x440000 0x20>;
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pin-count = <63>;
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max-func = <0xf>;
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cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 {
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marvell,pins = < 0 1 2 3 4 5 6 7
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8 9 10 11 >;
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marvell,function = <3>;
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};
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cps_spi1_pins: cps-spi-pins-1 {
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marvell,pins = < 13 14 15 16 >;
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marvell,function = <3>;
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};
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};
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cps_sata0: sata@540000 {
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compatible = "marvell,armada-8k-ahci";
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reg = <0x540000 0x30000>;
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@ -37,10 +37,10 @@ Example:
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pin-count = <20>;
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max-func = <3>;
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/* MPP Bus:
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SPI0 [0-3]
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I2C0 [4-5]
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UART0 [11,19]
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*/
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* SPI0 [0-3]
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* I2C0 [4-5]
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* UART0 [11,19]
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 3 3 3 3 3 3 0 0 0 0
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0 3 0 0 0 0 0 0 0 3>;
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@ -59,20 +59,20 @@ Example:
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pin-count = <63>;
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max-func = <0xf>;
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/* MPP Bus:
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[0-31] = 0xff: Keep default CP0_shared_pins:
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[11] CLKOUT_MPP_11 (out)
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[23] LINK_RD_IN_CP2CP (in)
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[25] CLKOUT_MPP_25 (out)
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[29] AVS_FB_IN_CP2CP (in)
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[32,34] SMI
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[31] GPIO: push button/Wake
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[35-36] GPIO
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[37-38] I2C
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[40-41] SATA[0/1]_PRESENT_ACTIVEn
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[42-43] XSMI
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[44-55] RGMII1
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[56-62] SD
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*/
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* [0-31] = 0xff: Keep default CP0_shared_pins:
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* [11] CLKOUT_MPP_11 (out)
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* [23] LINK_RD_IN_CP2CP (in)
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* [25] CLKOUT_MPP_25 (out)
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* [29] AVS_FB_IN_CP2CP (in)
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* [32,34] SMI
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* [31] GPIO: push button/Wake
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* [35-36] GPIO
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* [37-38] I2C
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* [40-41] SATA[0/1]_PRESENT_ACTIVEn
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* [42-43] XSMI
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* [44-55] RGMII1
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* [56-62] SD
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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@ -95,10 +95,10 @@ Example:
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pin-count = <63>;
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max-func = <0xf>;
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/* MPP Bus:
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[0-11] RGMII0
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[27,31] GE_MDIO/MDC
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[32-62] = 0xff: Keep default CP1_shared_pins:
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*/
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* [0-11] RGMII0
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* [27,31] GE_MDIO/MDC
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* [32-62] = 0xff: Keep default CP1_shared_pins:
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
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0x3 0x3 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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