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powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA 

Part of the SERDES9 erratum work-around is to set some bits in the SerDes
TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA.  The
current code does this only for XAUI, so extend it to the other protocols.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Timur Tabi 2011-04-14 15:37:06 -05:00 committed by Kumar Gala
parent 7d6d9ba9d0
commit f68d306349
2 changed files with 35 additions and 17 deletions
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51
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
View File

@ -549,6 +549,35 @@ void fsl_serdes_init(void)
printf("%s ", serdes_prtcl_str[lane_prtcl]); printf("%s ", serdes_prtcl_str[lane_prtcl]);
#endif #endif
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
/*
* Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for
* each of the SerDes lanes selected as SGMII, XAUI, SRIO, or
* AURORA before the device is initialized.
*/
switch (lane_prtcl) {
case SGMII_FM1_DTSEC1:
case SGMII_FM1_DTSEC2:
case SGMII_FM1_DTSEC3:
case SGMII_FM1_DTSEC4:
case SGMII_FM2_DTSEC1:
case SGMII_FM2_DTSEC2:
case SGMII_FM2_DTSEC3:
case SGMII_FM2_DTSEC4:
case XAUI_FM1:
case XAUI_FM2:
case SRIO1:
case SRIO2:
case AURORA:
clrsetbits_be32(&srds_regs->lane[idx].ttlcr0,
SRDS_TTLCR0_FLT_SEL_MASK,
SRDS_TTLCR0_FLT_SEL_750PPM |
SRDS_TTLCR0_PM_DIS);
default:
break;
}
#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
switch (lane_prtcl) { switch (lane_prtcl) {
case PCIE1: case PCIE1:
@ -595,24 +624,12 @@ void fsl_serdes_init(void)
FSL_CORENET_DEVDISR2_DTSEC2_4; FSL_CORENET_DEVDISR2_DTSEC2_4;
break; break;
case XAUI_FM1: case XAUI_FM1:
serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
FSL_CORENET_DEVDISR2_10GEC1;
break;
case XAUI_FM2: case XAUI_FM2:
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
/* FSL_CORENET_DEVDISR2_10GEC2;
* Set BnTTLCRy0[FLT_SEL] = 000011 and set
* BnTTLCRy0[17] = 1 for each of the SerDes lanes
* selected as XAUI on each bank before XAUI is
* initialized.
*/
clrsetbits_be32(&srds_regs->lane[idx].ttlcr0,
SRDS_TTLCR0_FLT_SEL_MASK,
0x03000000 | SRDS_TTLCR0_PM_DIS);
#endif
if (lane_prtcl == XAUI_FM1)
serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
FSL_CORENET_DEVDISR2_10GEC1;
else
serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
FSL_CORENET_DEVDISR2_10GEC2;
break; break;
case AURORA: case AURORA:
break; break;

1
arch/powerpc/include/asm/immap_85xx.h
View File

@ -2139,6 +2139,7 @@ typedef struct serdes_corenet {
u32 res3; u32 res3;
u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */ u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000 #define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
#define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
#define SRDS_TTLCR0_PM_DIS 0x00004000 #define SRDS_TTLCR0_PM_DIS 0x00004000
u32 res4[7]; u32 res4[7];
} lane[24]; } lane[24];