ARM: UniPhier: rename SC_CLKCTRL_CLK_* to SC_SCLKCTRL_CEN_*
Follow the register macros in the LSI specification book. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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27eac5df17
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f267b81e20
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@ -47,12 +47,12 @@
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#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
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#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
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#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
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#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
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#define SC_CLKCTRL_CLK_ETHER (0x1 << 12)
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#define SC_CLKCTRL_CEN_ETHER (0x1 << 12)
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#define SC_CLKCTRL_CLK_MIO (0x1 << 11)
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#define SC_CLKCTRL_CEN_MIO (0x1 << 11)
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#define SC_CLKCTRL_CLK_UMC (0x1 << 4)
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#define SC_CLKCTRL_CEN_UMC (0x1 << 4)
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#define SC_CLKCTRL_CLK_NAND (0x1 << 2)
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#define SC_CLKCTRL_CEN_NAND (0x1 << 2)
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#define SC_CLKCTRL_CLK_SBC (0x1 << 1)
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#define SC_CLKCTRL_CEN_SBC (0x1 << 1)
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#define SC_CLKCTRL_CLK_PERI (0x1 << 0)
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#define SC_CLKCTRL_CEN_PERI (0x1 << 0)
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/* System reset control register */
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/* System reset control register */
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#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
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#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
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@ -22,8 +22,8 @@ void clkrst_init(void)
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/* privide clocks */
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/* privide clocks */
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tmp = readl(SC_CLKCTRL);
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tmp = readl(SC_CLKCTRL);
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tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
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tmp |= SC_CLKCTRL_CEN_ETHER | SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_UMC
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| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
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| SC_CLKCTRL_CEN_NAND | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
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writel(tmp, SC_CLKCTRL);
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writel(tmp, SC_CLKCTRL);
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readl(SC_CLKCTRL); /* dummy read */
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readl(SC_CLKCTRL); /* dummy read */
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}
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}
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@ -22,8 +22,8 @@ void clkrst_init(void)
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/* privide clocks */
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/* privide clocks */
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tmp = readl(SC_CLKCTRL);
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tmp = readl(SC_CLKCTRL);
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tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
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tmp |= SC_CLKCTRL_CEN_ETHER | SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_UMC
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| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
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| SC_CLKCTRL_CEN_NAND | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
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writel(tmp, SC_CLKCTRL);
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writel(tmp, SC_CLKCTRL);
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readl(SC_CLKCTRL); /* dummy read */
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readl(SC_CLKCTRL); /* dummy read */
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}
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}
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@ -17,7 +17,7 @@
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ENTRY(setup_lowlevel_debug)
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ENTRY(setup_lowlevel_debug)
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ldr r0, =SC_CLKCTRL
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ldr r0, =SC_CLKCTRL
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ldr r1, [r0]
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ldr r1, [r0]
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orr r1, r1, #SC_CLKCTRL_CLK_PERI
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orr r1, r1, #SC_CLKCTRL_CEN_PERI
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str r1, [r0]
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str r1, [r0]
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init_debug_uart r0, r1, r2
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init_debug_uart r0, r1, r2
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@ -22,8 +22,8 @@ void clkrst_init(void)
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/* privide clocks */
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/* privide clocks */
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tmp = readl(SC_CLKCTRL);
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tmp = readl(SC_CLKCTRL);
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tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
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tmp |= SC_CLKCTRL_CEN_ETHER | SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_UMC
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| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
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| SC_CLKCTRL_CEN_NAND | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
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writel(tmp, SC_CLKCTRL);
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writel(tmp, SC_CLKCTRL);
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readl(SC_CLKCTRL); /* dummy read */
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readl(SC_CLKCTRL); /* dummy read */
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}
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}
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