net: phy: micrel: center FLP burst timing at 16ms
Like [1], reset the FLP burst timing for the KSZ9031 to the 16ms specified by the IEEE802.3 standard from the chip's default of 8ms. For more details, see the "Auto-Negotiation Timing" section of the KSZ9031RNX datasheet. [1] https://patchwork.kernel.org/patch/6558371/ Signed-off-by: Ash Charles <ash.charles@savoirfairelinux.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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@ -415,11 +415,31 @@ static int ksz9031_of_config(struct phy_device *phydev)
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return 0;
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return 0;
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}
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}
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static int ksz9031_center_flp_timing(struct phy_device *phydev)
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{
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struct phy_driver *drv = phydev->drv;
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int ret = 0;
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if (!drv || !drv->writeext)
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return -EOPNOTSUPP;
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ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
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if (ret)
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return ret;
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ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
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return ret;
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}
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#else
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#else
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static int ksz9031_of_config(struct phy_device *phydev)
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static int ksz9031_of_config(struct phy_device *phydev)
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{
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{
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return 0;
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return 0;
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}
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}
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static int ksz9031_center_flp_timing(struct phy_device *phydev)
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{
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return 0;
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}
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#endif
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#endif
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/* Accessors to extended registers*/
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/* Accessors to extended registers*/
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@ -470,6 +490,9 @@ static int ksz9031_config(struct phy_device *phydev)
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{
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{
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int ret;
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int ret;
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ret = ksz9031_of_config(phydev);
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ret = ksz9031_of_config(phydev);
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if (ret)
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return ret;
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ret = ksz9031_center_flp_timing(phydev);
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if (ret)
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if (ret)
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return ret;
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return ret;
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return genphy_config(phydev);
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return genphy_config(phydev);
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@ -20,6 +20,9 @@
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#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6
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#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6
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#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8
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#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8
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#define MII_KSZ9031_FLP_BURST_TX_LO 0x3
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#define MII_KSZ9031_FLP_BURST_TX_HI 0x4
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/* Registers */
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/* Registers */
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#define MMD_ACCESS_CONTROL 0xd
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#define MMD_ACCESS_CONTROL 0xd
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#define MMD_ACCESS_REG_DATA 0xe
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#define MMD_ACCESS_REG_DATA 0xe
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