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x86: Clean up ivybridge/chrome Kconfig options 

There are some options which are never used, and also some options
which are selected by others but have never been a Kconfg option.
Clean these up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2015-11-25 17:46:07 -08:00
parent 9bf76c21e0
commit efe2d80cca
4 changed files with 0 additions and 33 deletions
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30
arch/x86/cpu/ivybridge/Kconfig
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@ -8,18 +8,9 @@
config NORTHBRIDGE_INTEL_IVYBRIDGE config NORTHBRIDGE_INTEL_IVYBRIDGE
bool bool
select CACHE_MRC_BIN select CACHE_MRC_BIN
select CPU_INTEL_MODEL_306AX
if NORTHBRIDGE_INTEL_IVYBRIDGE if NORTHBRIDGE_INTEL_IVYBRIDGE
config VGA_BIOS_ID
string
default "8086,0166"
config EXTERNAL_MRC_BLOB
bool
default n
config CACHE_MRC_SIZE_KB config CACHE_MRC_SIZE_KB
int int
default 512 default 512
@ -50,24 +41,9 @@ config DCACHE_RAM_MRC_VAR_SIZE
memory reference code. This should be set to 16KB (0x4000 hex) memory reference code. This should be set to 16KB (0x4000 hex)
so that MRC has enough space to run. so that MRC has enough space to run.
config MRC_FILE
string "Intel System Agent path and filename"
depends on HAVE_MRC
default "systemagent-ivybridge.bin"
help
The path and filename of the file to use as System Agent
binary.
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select SMM_TSEG select SMM_TSEG
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SSE2
select UDELAY_LAPIC
select CPU_MICROCODE_IN_CBFS
select TSC_SYNC_MFENCE
select HAVE_INTEL_ME select HAVE_INTEL_ME
select X86_RAMTEST select X86_RAMTEST
@ -99,12 +75,6 @@ config CPU_INTEL_SOCKET_RPGA989
if CPU_INTEL_SOCKET_RPGA989 if CPU_INTEL_SOCKET_RPGA989
config SOCKET_SPECIFIC_OPTIONS # dummy
def_bool y
select MMX
select SSE
select CACHE_AS_RAM
config CACHE_MRC_BIN config CACHE_MRC_BIN
bool bool
default n default n

1
board/google/chromebook_link/Kconfig
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@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select X86_RESET_VECTOR select X86_RESET_VECTOR
select CPU_INTEL_SOCKET_RPGA989 select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE select NORTHBRIDGE_INTEL_IVYBRIDGE
select SOUTHBRIDGE_INTEL_C216
select HAVE_ACPI_RESUME select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_8192 select BOARD_ROMSIZE_KB_8192

1
board/google/chromebox_panther/Kconfig
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@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select X86_RESET_VECTOR select X86_RESET_VECTOR
select CPU_INTEL_SOCKET_RPGA989 select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE select NORTHBRIDGE_INTEL_IVYBRIDGE
select SOUTHBRIDGE_INTEL_C216
select HAVE_ACPI_RESUME select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_8192 select BOARD_ROMSIZE_KB_8192

1
include/configs/x86-chromebook.h
View File

@ -14,7 +14,6 @@
#define CONFIG_MISC_INIT_R #define CONFIG_MISC_INIT_R
#define CONFIG_X86_MRC_ADDR 0xfffa0000 #define CONFIG_X86_MRC_ADDR 0xfffa0000
#define CONFIG_CACHE_MRC_SIZE_KB 512
#define CONFIG_SCSI_DEV_LIST \ #define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \