Clean up the code according to codestyle:
(1) remove some C++ comments.
(2) remove trailing white space.
(3) remove trailing empty line.
(4) Indentation by table.
(5) remove {} in one line condition.
(6) add space before '(' in function call.
Remove some weird printf () output.
Add necessary comments.
Modified Makefile to support building in a separate directory.
This commit is contained in:
roy zang
Zang Tiefei
parent
6bd87c0aee
commit
ee311214e0
2
Makefile
2
Makefile
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@ -1722,7 +1722,7 @@ EVB64260_750CX_config: unconfig
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@$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260
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mpc7448hpc2_config: unconfig
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@./mkconfig $(@:_config=) ppc 74xx_7xx mpc7448hpc2
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@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2
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P3G4_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260
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@ -23,26 +23,30 @@
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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LIB = $(obj)lib$(BOARD).a
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OBJS = $(BOARD).o tsi108_init.o
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COBJS := $(BOARD).o tsi108_init.o
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SOBJS := asm_init.o
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SOBJS = asm_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): .depend $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS) $(SOBJS)
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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.PHONY: distclean
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude .depend
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sinclude ($obj).depend
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#########################################################################
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@ -1,4 +1,4 @@
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/*****************************************************************************
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/*
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* (C) Copyright 2004-05; Tundra Semiconductor Corp.
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*
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* Added automatic detect of SDC settings
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@ -19,9 +19,9 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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****************************************************************************/
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*/
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/*----------------------------------------------------------------------------
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/*
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* FILENAME: asm_init.s
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*
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* Originator: Alex Bounine
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@ -29,7 +29,7 @@
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* DESCRIPTION:
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* Initialization code for the Tundra Tsi108 bridge chip
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*
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*---------------------------------------------------------------------------*/
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*/
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#include <config.h>
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#include <version.h>
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@ -40,7 +40,7 @@
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#include <tsi108.h>
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/*===========================================================================
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/*
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* Build Configuration Options
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*/
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@ -48,7 +48,7 @@
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/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */
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/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */
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/* ===========================================================================
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/*
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* Hardcoded SDC settings
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*/
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@ -65,24 +65,24 @@
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#endif /* SDC_HARDCODED_INIT */
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/*---------------------------------------------------------------------------
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/*
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CPU Configuration:
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CPU Address and Data Parity enables.
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#define CPU_AP
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#define CPU_DP
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*/
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===========================================================================
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Macros
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!!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are
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expected to work correctly for the CSR space within 32KB range.
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LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant.
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These macros are absolutely identical except their names. This difference
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is provided intentionally for better readable code.
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-------------------------------------------------------------------------*/
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/*
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* Macros
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* !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are
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* expected to work correctly for the CSR space within 32KB range.
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*
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* LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant.
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* These macros are absolutely identical except their names. This difference
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* is provided intentionally for better readable code.
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*/
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#define LOAD_PTR(reg,const32) \
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addis reg,r0,const32@h; ori reg,reg,const32@l
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@ -90,8 +90,9 @@
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#define LOAD_U32(reg,const32) \
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addis reg,r0,const32@h; ori reg,reg,const32@l
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/* LOADMEM initializes a register with the contents of a specified 32-bit memory
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location, usually a CSR value.*/
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/* LOADMEM initializes a register with the contents of a specified 32-bit
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* memory location, usually a CSR value.
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*/
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#define LOAD_MEM(reg,addr32) \
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addis reg,r0,addr32@ha; lwz reg,addr32@l(reg)
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@ -102,37 +103,30 @@ sdc_clk_sync:
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.long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */
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#endif
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/*===========================================================================
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board_asm_init() - early initialization function. Coded to be portable to
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dual-CPU configuration.
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Checks CPU number and performs board HW initialization if called for CPU0.
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Registers used: r3,r4,r5,r6,r19,r29
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===========================================================================
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---------------------------------------------------------------------------
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NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108
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and the rest of the board. Current implementation demonstrates two
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possible ways to identify CPU number:
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- for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM.
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- for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108.
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---------------------------------------------------------------------------*/
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/*
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* board_asm_init() - early initialization function. Coded to be portable to
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* dual-CPU configuration.
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* Checks CPU number and performs board HW initialization if called for CPU0.
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* Registers used: r3,r4,r5,r6,r19,r29
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*
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* NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108
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* and the rest of the board. Current implementation demonstrates two
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* possible ways to identify CPU number:
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* - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM.
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* - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108.
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*/
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.globl board_asm_init
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board_asm_init:
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mflr r19 /* Save LR to be able return later. */
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bl icache_enable /* Enable icache to reduce reads from flash. */
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/* Initialize pointer to Tsi108 register space
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-------------------------------------------------------------------------*/
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/* Initialize pointer to Tsi108 register space */
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LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
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ori r4,r29,TSI108_PB_REG_OFFSET
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/*-------------------------------------------------------------------------
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Check Processor Version Number */
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/* Check Processor Version Number */
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mfspr r3, PVR
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rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */
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@ -140,10 +134,10 @@ board_asm_init:
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cmpli 0,0,r3,0x8000 /* MPC74xx */
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bne cont_brd_init
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/* ------------------------------------------
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For MPC744x/5x enable extended BATs[4-7]
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Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1
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to disable prefetch
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/*
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* For MPC744x/5x enable extended BATs[4-7]
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* Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1
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* to disable prefetch
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*/
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mfspr r5, HID0
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@ -167,11 +161,10 @@ board_asm_init:
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isync
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sync
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#if(1) /* def CONFIG_DUAL_CPU
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-------------------------------------------------------------------------
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For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number.
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/* def CONFIG_DUAL_CPU
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* For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number.
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*/
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#if(1)
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mfspr r3,1014 /* read MSSCR0 */
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rlwinm. r3,r3,27,31,31 /* get processor ID number */
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mtspr SPRN_PIR,r3 /* Save CPU ID */
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@ -182,33 +175,29 @@ board_asm_init:
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cont_brd_init:
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/* An alternative method of checking the processor number (in addition
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to configuration using MSSCR0[ID] bit on MPC74xx).
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Good for IBM PPC750FX/GX.
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* to configuration using MSSCR0[ID] bit on MPC74xx).
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* Good for IBM PPC750FX/GX.
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*/
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lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */
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rlwinm. r3,r3,24,31,31 /* get processor ID number */
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bne init_done
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#else
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cont_brd_init:
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#endif /* CONFIG_DUAL_CPU */
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/* Initialize Tsi108 chip
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---------------------------------------------------------------------------
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*/
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/* Initialize Tsi108 chip */
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do_tsi108_init:
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/*--------------------------------------------------------------------------
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Adjust HLP/Flash parameters. By default after reset the HLP port is set
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to support slow devices. Better performance can be achived when an optimal
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parameters are used for specific EPROM device.
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NOTE: This should be performed ASAP for the emulation platform because
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it has 5MHz HLP clocking.
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/*
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* Adjust HLP/Flash parameters. By default after reset the HLP port is
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* set to support slow devices. Better performance can be achived when
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* an optimal parameters are used for specific EPROM device.
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* NOTE: This should be performed ASAP for the emulation platform
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* because it has 5MHz HLP clocking.
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*/
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#ifdef CONFIG_TSI108EMU
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@ -221,28 +210,25 @@ do_tsi108_init:
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sync
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#endif
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/* -------------------------------------------------------------------------
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* Initialize PB interface.
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*/
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/* Initialize PB interface. */
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ori r4,r29,TSI108_PB_REG_OFFSET
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#if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE)
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/* Relocate (if required) Tsi108 registers. Set new value for PB_REG_BAR:
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/* Relocate (if required) Tsi108 registers. Set new value for
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* PB_REG_BAR:
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* Note we are in the 32-bit address mode.
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*/
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LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* value for PB_REG_BAR: BA + EN*/
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LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
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stw r5,PB_REG_BAR(r4)
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andis. r29,r5,0xFFFF
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sync
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ori r4,r29,TSI108_PB_REG_OFFSET
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#endif
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/* Set PB Slave configuration register */
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/* LOAD_U32(r5,0x000024C7) value for PB_SCR: TEA enabled,AACK delay = 7 */
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LOAD_U32(r5,0x00002481) /* value for PB_SCR: TEA enabled,AACK delay = 1 */
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LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */
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lwz r3, PB_RSR(r4) /* get PB bus mode */
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xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */
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rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */
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@ -257,10 +243,7 @@ do_tsi108_init:
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ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */
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#endif
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andc r5,r5,r3 /* Clear the masked bit fields */
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/* ori r5,r5,0x0040 Set pipeline depth 4
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ori r5,r5,0x0080 Set pipeline depth 8
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ori r5,r5,0x0020 !!!avb Testing: set pipeline depth 2 */
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ori r5,r5,0x0001
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ori r5,r5,0x0001 /* Set pipeline depth */
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stw r5,PB_ARB_CTRL(r4)
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#if (0) /* currently using the default settings for PBM after reset */
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@ -274,9 +257,9 @@ do_tsi108_init:
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#endif
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/* Disable or enable PVT based on processor bus frequency
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1. Read CG_PWRUP_STATUS register field bits 18,17,16
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2. See if the value is < or > 133mhz (18:16 = 100)
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3. If > enable PVT
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* 1. Read CG_PWRUP_STATUS register field bits 18,17,16
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* 2. See if the value is < or > 133mhz (18:16 = 100)
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* 3. If > enable PVT
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*/
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LOAD_U32(r3,0xC0002234)
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@ -293,9 +276,7 @@ do_tsi108_init:
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sync
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#endif
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/*---------------------------------------------------------------------------
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Initialize SDRAM controller.
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----------------------------------------------------------------------------*/
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/* Initialize SDRAM controller. */
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sdc_init:
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@ -337,7 +318,8 @@ get_nsec:
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#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */
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/* First read the CG_PWRUP_STATUS register to get the
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memory speed from bits 22,21,20 */
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* memory speed from bits 22,21,20
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*/
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LOAD_U32(r3,0xC0002234)
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lwz r3,0(r3)
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@ -348,9 +330,9 @@ get_nsec:
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cmpi 0,0,r3,0x0005
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bne check_for_200mhz
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/* set values for 166 Mhz memory speed */
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/* Set refresh rate and timing parameters */
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/* set values for 166 Mhz memory speed
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* Set refresh rate and timing parameters
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*/
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LOAD_U32(r5,0x00000515)
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stw r5,SD_REFRESH(r4)
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LOAD_U32(r5,0x03073368)
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@ -386,9 +368,9 @@ check_for_200mhz:
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cmpi 0,0,r3,0x0006
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bne set_default_values
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/* set values for 200Mhz memory speed */
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/* Set refresh rate and timing parameters */
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/* set values for 200Mhz memory speed
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* Set refresh rate and timing parameters
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*/
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LOAD_U32(r5,0x0000061a)
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stw r5,SD_REFRESH(r4)
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LOAD_U32(r5,0x03083348)
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@ -449,11 +431,8 @@ set_default_values:
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LOAD_U32(r5,VAL_SD_D1_BAR)
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stw r5,SD_D1_BAR(r4)
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sync
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#else /* !SDC_HARDCODED_INIT */
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bl tsi108_sdram_spd /* automatically detect SDC settings */
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#endif /* SDC_HARDCODED_INIT */
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sdc_init_done:
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@ -481,43 +460,47 @@ sdc_init_done:
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wait_init_complete:
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lwz r5,SD_STATUS(r4)
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andi. r5,r5,0x0001
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beq wait_init_complete /* wait until SDRAM initialization is complete */
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/* wait until SDRAM initialization is complete */
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beq wait_init_complete
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/*---------------------------------------------------------------------------
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Map SDRAM into the processor bus address space
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---------------------------------------------------------------------------*/
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/* Map SDRAM into the processor bus address space */
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ori r4,r29,TSI108_PB_REG_OFFSET
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/* Setup BARs associated with direct path PB<->SDRAM */
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/* PB_SDRAM_BAR1:
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provides a direct path to the main system memory (cacheable SDRAM) */
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* provides a direct path to the main system memory (cacheable SDRAM)
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*/
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LOAD_U32(r5, 0x00000011) /* BA=0,Size=512MB, ENable, No Addr.Translation */
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/* BA=0,Size=512MB, ENable, No Addr.Translation */
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LOAD_U32(r5, 0x00000011)
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stw r5,PB_SDRAM_BAR1(r4)
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sync
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/* Make sure that PB_SDRAM_BAR1 decoder is set
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(to allow following immediate read from SDRAM) */
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* (to allow following immediate read from SDRAM)
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*/
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lwz r5,PB_SDRAM_BAR1(r4)
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sync
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/* PB_SDRAM_BAR2:
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provides non-cacheable alias (via the direct path) to main system memory.
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Size = 512MB, ENable, Addr.Translation - ON,
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BA = 0x0_40000000, TA = 0x0_00000000 */
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* provides non-cacheable alias (via the direct path) to main
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* system memory.
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* Size = 512MB, ENable, Addr.Translation - ON,
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* BA = 0x0_40000000, TA = 0x0_00000000
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*/
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LOAD_U32(r5, 0x40010011)
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stw r5,PB_SDRAM_BAR2(r4)
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sync
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/* Make sure that PB_SDRAM_BAR2 decoder is set
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(to allow following immediate read from SDRAM) */
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* (to allow following immediate read from SDRAM)
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*/
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lwz r5,PB_SDRAM_BAR2(r4)
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sync
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init_done:
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/* All done. Restore LR and return. */
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@ -525,11 +508,11 @@ init_done:
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blr
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#if (0)
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/*===========================================================================
|
||||
init_cpu1
|
||||
|
||||
This routine enables CPU1 on the dual-processor system.
|
||||
===========================================================================*/
|
||||
/*
|
||||
* init_cpu1
|
||||
* This routine enables CPU1 on the dual-processor system.
|
||||
* Now there is only one processor in the system
|
||||
*/
|
||||
|
||||
.global enable_cpu1
|
||||
enable_cpu1:
|
||||
|
|
@ -545,11 +528,10 @@ enable_cpu1:
|
|||
blr
|
||||
#endif
|
||||
|
||||
/*===========================================================================
|
||||
enable_EI
|
||||
|
||||
Enable CPU core external interrupt
|
||||
===========================================================================*/
|
||||
/*
|
||||
* enable_EI
|
||||
* Enable CPU core external interrupt
|
||||
*/
|
||||
|
||||
.global enable_EI
|
||||
enable_EI:
|
||||
|
|
@ -558,11 +540,10 @@ enable_EI:
|
|||
mtmsr r3
|
||||
blr
|
||||
|
||||
/*===========================================================================
|
||||
disable_EI
|
||||
|
||||
Disable CPU core external interrupt
|
||||
===========================================================================*/
|
||||
/*
|
||||
* disable_EI
|
||||
* Disable CPU core external interrupt
|
||||
*/
|
||||
|
||||
.global disable_EI
|
||||
disable_EI:
|
||||
|
|
@ -573,11 +554,7 @@ disable_EI:
|
|||
blr
|
||||
|
||||
#ifdef ENABLE_SDRAM_ECC
|
||||
/*===========================================================================
|
||||
enable_ECC
|
||||
|
||||
enables SDRAM ECC
|
||||
===========================================================================*/
|
||||
/* enables SDRAM ECC */
|
||||
|
||||
.global enable_ECC
|
||||
enable_ECC:
|
||||
|
|
@ -587,17 +564,15 @@ enable_ECC:
|
|||
stw r3,SD_ECC_CTRL(r4)
|
||||
blr
|
||||
|
||||
/*===========================================================================
|
||||
clear_ECC_err
|
||||
|
||||
Clears all pending SDRAM ECC errors
|
||||
(normally after SDRAM scrubbing/initialization)
|
||||
===========================================================================*/
|
||||
/*
|
||||
* clear_ECC_err
|
||||
* Clears all pending SDRAM ECC errors
|
||||
* (normally after SDRAM scrubbing/initialization)
|
||||
*/
|
||||
|
||||
.global clear_ECC_err
|
||||
clear_ECC_err:
|
||||
ori r4,r29,TSI108_SD_REG_OFFSET
|
||||
/* lwz r3,SD_INT_STATUS(r4) Read SDRAM ECC Control Register */
|
||||
ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */
|
||||
stw r3,SD_INT_STATUS(r4)
|
||||
blr
|
||||
|
|
@ -606,10 +581,7 @@ clear_ECC_err:
|
|||
|
||||
#ifndef SDC_HARDCODED_INIT
|
||||
|
||||
/********************************************************************
|
||||
* SDRAM SPD Support
|
||||
*/
|
||||
|
||||
/* SDRAM SPD Support */
|
||||
#define SD_I2C_CTRL1 (0x400)
|
||||
#define SD_I2C_CTRL2 (0x404)
|
||||
#define SD_I2C_RD_DATA (0x408)
|
||||
|
|
@ -682,14 +654,14 @@ refresh_rates: /* in nSec */
|
|||
.long 62500 /* Extended 4x (0x84) */
|
||||
.long 125000 /* Extended 8x (0x85) */
|
||||
|
||||
/*===========================================================================
|
||||
/*
|
||||
* tsi108_sdram_spd
|
||||
*
|
||||
* Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data
|
||||
* Uses registers: r4 - SDC base address (not changed)
|
||||
* r9 - SDC clocking period in nSec
|
||||
* Changes registers: r3,r5,r6,r7,r8,r10,r11
|
||||
*==========================================================================*/
|
||||
*/
|
||||
|
||||
tsi108_sdram_spd:
|
||||
|
||||
|
|
@ -698,9 +670,7 @@ tsi108_sdram_spd:
|
|||
|
||||
do_first_dimm:
|
||||
|
||||
/**************************************
|
||||
* Program Refresh Rate Register
|
||||
*/
|
||||
/* Program Refresh Rate Register */
|
||||
|
||||
READ_SPD(12) /* get Refresh Rate */
|
||||
beq check_next_slot
|
||||
|
|
@ -718,9 +688,7 @@ do_first_dimm:
|
|||
stw r5,SD_REFRESH(r4) /* Set refresh rate */
|
||||
sync
|
||||
|
||||
/**************************************
|
||||
* Program SD Timing Register
|
||||
*/
|
||||
/* Program SD Timing Register */
|
||||
|
||||
li r7, 0 /* clear r7 prior parameter collection */
|
||||
|
||||
|
|
@ -768,7 +736,8 @@ set_tras:
|
|||
|
||||
READ_SPD(29) /* Get tRCD */
|
||||
beq spd_read_fail
|
||||
rlwinm r3,r3,30,2,31/* right shift tRCD by 2 bits as per DDR2 spec */
|
||||
/* right shift tRCD by 2 bits as per DDR2 spec */
|
||||
rlwinm r3,r3,30,2,31
|
||||
divwu r6,r3,r9
|
||||
mullw r8,r6,r9
|
||||
subf. r8,r8,r3
|
||||
|
|
@ -829,17 +798,14 @@ set_trfc:
|
|||
stw r7,SD_TIMING(r4)
|
||||
sync
|
||||
|
||||
/*=====================================================================
|
||||
/*
|
||||
* The following two registers are set on per-DIMM basis.
|
||||
* The SD_REFRESH and SD_TIMING settings are common for both DIMMS
|
||||
*=====================================================================
|
||||
*/
|
||||
|
||||
do_each_dimm:
|
||||
|
||||
/*****************************************
|
||||
* Program SDRAM DIMM Control Register
|
||||
*/
|
||||
/* Program SDRAM DIMM Control Register */
|
||||
|
||||
li r7, 0 /* clear r7 prior parameter collection */
|
||||
|
||||
|
|
@ -897,9 +863,7 @@ set_dimm_ctrl:
|
|||
sync
|
||||
|
||||
|
||||
/********************************************
|
||||
* Program SDRAM DIMMx Base Address Register
|
||||
*/
|
||||
/* Program SDRAM DIMMx Base Address Register */
|
||||
|
||||
set_dimm_bar:
|
||||
READ_SPD(5) /* get # of Ranks */
|
||||
|
|
@ -952,4 +916,3 @@ err_hung: /* hang here for debugging */
|
|||
b err_hung
|
||||
|
||||
#endif /* !SDC_HARDCODED_INIT */
|
||||
|
||||
|
|
|
|||
|
|
@ -57,7 +57,6 @@ void after_reloc(ulong dest_addr)
|
|||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*
|
||||
* report board type
|
||||
*/
|
||||
|
||||
|
|
@ -369,10 +368,9 @@ int mem_test_walk(void)
|
|||
|
||||
for (i = 0; i < 63; i++) {
|
||||
printf ("Pass %2d", i + 2);
|
||||
if (mem_march(pmem, size, mask, mask << 1, 1, 1) != 0) {
|
||||
if (mem_march(pmem, size, mask, mask << 1, 1, 1) != 0)
|
||||
/*printf ("mask: 0x%x, pass: %d, ", mask, i); */
|
||||
return 1;
|
||||
}
|
||||
mask = mask << 1;
|
||||
printf ("\b\b\b\b\b\b\b");
|
||||
}
|
||||
|
|
@ -428,11 +426,10 @@ int testdram(void)
|
|||
/* runaddress = 0; */
|
||||
/* runwalk = 0; */
|
||||
|
||||
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
|
||||
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
|
||||
printf ("Testing RAM from 0x%08x to 0x%08x ... \
|
||||
(don't panic... that will take a moment !!!!)\n", \
|
||||
CFG_MEMTEST_START, CFG_MEMTEST_END);
|
||||
}
|
||||
#ifdef CFG_DRAM_TEST_DATA
|
||||
if (rundata == 1) {
|
||||
printf ("Test DATA ... ");
|
||||
|
|
@ -463,9 +460,8 @@ int testdram(void)
|
|||
printf ("ok \n");
|
||||
}
|
||||
#endif
|
||||
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
|
||||
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
|
||||
printf ("passed\n");
|
||||
}
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -145,26 +145,27 @@ int board_early_init_f(void)
|
|||
ulong i;
|
||||
|
||||
gd->mem_clk = 0;
|
||||
i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
|
||||
i = (i >> 20) & 0x07;
|
||||
i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
|
||||
CG_PWRUP_STATUS);
|
||||
i = (i >> 20) & 0x07; /* value of SW4[4:7] */
|
||||
switch (i) {
|
||||
case 0:
|
||||
case 0: /* external clock */
|
||||
printf ("Using external clock\n");
|
||||
break;
|
||||
case 1:
|
||||
case 1: /* system clock */
|
||||
gd->mem_clk = gd->bus_clk;
|
||||
break;
|
||||
case 4:
|
||||
case 5:
|
||||
case 6:
|
||||
case 4: /* 133 MHz */
|
||||
case 5: /* 166 MHz */
|
||||
case 6: /* 200 MHz */
|
||||
gd->mem_clk = pb_clk_sel[i] * 1000000;
|
||||
break;
|
||||
default:
|
||||
printf ("Invalid DDR2 clock setting\n");
|
||||
return -1;
|
||||
}
|
||||
printf("BUS! %d MHz\n", get_board_bus_clk() / 1000000);
|
||||
printf("MEM! %d MHz\n", gd->mem_clk / 1000000);
|
||||
printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000);
|
||||
printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -338,10 +339,9 @@ int board_early_init_r(void)
|
|||
|
||||
temp = get_cpu_type ();
|
||||
|
||||
if ((CPU_750FX == temp) || (CPU_750GX == temp)) {
|
||||
if ((CPU_750FX == temp) || (CPU_750GX == temp))
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
|
||||
0x00009955);
|
||||
}
|
||||
#endif /* DISABLE_PBM */
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
|
|
@ -350,8 +350,8 @@ int board_early_init_r(void)
|
|||
*/
|
||||
|
||||
/* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
|
||||
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0_UPPER,
|
||||
0);
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
|
||||
PCI_PFAB_BAR0_UPPER, 0);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
|
||||
|
|
@ -360,8 +360,8 @@ int board_early_init_r(void)
|
|||
|
||||
/* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
|
||||
|
||||
temp =
|
||||
in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
|
||||
temp = in32(CFG_TSI108_CSR_BASE +
|
||||
TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
|
||||
|
||||
temp &= ~0xFF00; /* Clear the BUS_NUM field */
|
||||
|
||||
|
|
@ -510,8 +510,8 @@ int board_early_init_r(void)
|
|||
#ifdef ENABLE_PCI_CSR_BAR
|
||||
/* open if required access to Tsi108 CSRs from the PCI/X bus */
|
||||
/* enable BAR0 on the PCI/X bus */
|
||||
reg_val =
|
||||
in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
|
||||
reg_val = in32(CFG_TSI108_CSR_BASE +
|
||||
TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
|
||||
reg_val |= 0x02;
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
|
||||
reg_val);
|
||||
|
|
@ -595,8 +595,10 @@ int misc_init_r(void)
|
|||
* Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
|
||||
*/
|
||||
|
||||
out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0x002e0044); /* D = 0.25% */
|
||||
out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1, 0x00000039); /* BWADJ */
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
|
||||
0x002e0044); /* D = 0.25% */
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
|
||||
0x00000039); /* BWADJ */
|
||||
|
||||
/* Initialize PLL0: CG_PB_CLKO */
|
||||
/* Detect PB clock freq. */
|
||||
|
|
@ -610,7 +612,8 @@ int misc_init_r(void)
|
|||
|
||||
/* Wait and set SSEN for both PLL0 and 1 */
|
||||
udelay (1000);
|
||||
out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0x802e0044); /* D=0.25% */
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
|
||||
0x802e0044); /* D=0.25% */
|
||||
out32 (CFG_TSI108_CSR_BASE +
|
||||
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
|
||||
0x80000000 | pll0_config[i].ctrl0);
|
||||
|
|
|
|||
|
|
@ -127,16 +127,17 @@ int get_clocks (void)
|
|||
ulong clock = 0;
|
||||
|
||||
#ifdef CFG_CONFIG_BUS_CLK
|
||||
gd->bus_clk = get_board_bus_clk();
|
||||
gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */
|
||||
#else
|
||||
gd->bus_clk = CFG_BUS_CLK;
|
||||
gd->bus_clk = CFG_BUS_CLK; /* bus clock is a fixed frequency */
|
||||
#endif
|
||||
|
||||
/* calculate the clock frequency based upon the CPU type */
|
||||
switch (get_cpu_type()) {
|
||||
case CPU_7447A:
|
||||
case CPU_7448:
|
||||
clock = (gd->bus_clk / 10) * hid1_7447A_multipliers_x_10[(get_hid1 () >> 12) & 0x1F];
|
||||
clock = (gd->bus_clk / 10) *
|
||||
hid1_7447A_multipliers_x_10[(get_hid1 () >> 12) & 0x1F];
|
||||
break;
|
||||
|
||||
case CPU_7455:
|
||||
|
|
@ -146,12 +147,14 @@ int get_clocks (void)
|
|||
* Make sure division is done before multiplication to prevent 32-bit
|
||||
* arithmetic overflows which will cause a negative number
|
||||
*/
|
||||
clock = (gd->bus_clk / 10) * hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF];
|
||||
clock = (gd->bus_clk / 10) *
|
||||
hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF];
|
||||
break;
|
||||
|
||||
case CPU_750GX:
|
||||
case CPU_750FX:
|
||||
clock = gd->bus_clk * hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
|
||||
clock = gd->bus_clk *
|
||||
hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
|
||||
break;
|
||||
|
||||
case CPU_7450:
|
||||
|
|
@ -168,7 +171,8 @@ int get_clocks (void)
|
|||
* Make sure division is done before multiplication to prevent 32-bit
|
||||
* arithmetic overflows which will cause a negative number
|
||||
*/
|
||||
clock = (gd->bus_clk / 10) * hid1_multipliers_x_10[get_hid1 () >> 28];
|
||||
clock = (gd->bus_clk / 10) *
|
||||
hid1_multipliers_x_10[get_hid1 () >> 28];
|
||||
break;
|
||||
|
||||
case CPU_UNKNOWN:
|
||||
|
|
|
|||
|
|
@ -39,7 +39,6 @@ The mapping is:
|
|||
0xff00_0000 0xff80_0000 FLASH (boot flash) 8M
|
||||
0xff80_0000 0xffff_ffff FLASH (second half flash) 8M
|
||||
|
||||
|
||||
Using Flash
|
||||
-----------
|
||||
|
||||
|
|
@ -67,16 +66,13 @@ it into the secondary bank:
|
|||
erase ff000000 ff080000
|
||||
cp.b 10000 ff000000 80000
|
||||
|
||||
|
||||
After copying the image into the second bank of flash, be sure to toggle
|
||||
SW3[4] on board before resetting the board in order to set the
|
||||
secondary bank as the boot-bank.
|
||||
|
||||
|
||||
Board Switches
|
||||
----------------------
|
||||
|
||||
|
||||
Most switches on the board should not be changed. The most frequent
|
||||
user-settable switches on the board are used to configure
|
||||
the flash banks and determining the PCI frequency.
|
||||
|
|
@ -111,7 +107,6 @@ SW2[1-6]: CPU core frequency
|
|||
This table shows only a subset of available frequency options; see the CPU
|
||||
hardware specifications for more information.
|
||||
|
||||
|
||||
SW2[7-8]: Bus Protocol and CPU Reset Option
|
||||
|
||||
7
|
||||
|
|
@ -124,7 +119,6 @@ SW2[7-8]: Bus Protocol and CPU Reset Option
|
|||
SW2=0 TSI108 can cause CPU reset
|
||||
SW2=1 TSI108 can not cause CPU reset
|
||||
|
||||
|
||||
SW3[1-8] system options
|
||||
|
||||
123
|
||||
|
|
@ -167,7 +161,6 @@ SW4[1-3]: System bus frequency
|
|||
SW4=110 200 only for MPC7448
|
||||
others reserved
|
||||
|
||||
|
||||
SW4[4-6]: DDR2 SDRAM frequency
|
||||
|
||||
Bus Frequency (MHz)
|
||||
|
|
@ -179,7 +172,6 @@ SW4[4-6]: DDR2 SDRAM frequency
|
|||
SW4=110 200
|
||||
others reserved
|
||||
|
||||
|
||||
SW4[7-8]: PCI/PCI-X frequency control
|
||||
7
|
||||
-
|
||||
|
|
|
|||
|
|
@ -46,7 +46,9 @@
|
|||
#endif
|
||||
|
||||
#if TSI108_ETH_DEBUG > 0
|
||||
#define debug_lev(lev, fmt, args...) if (lev <= TSI108_ETH_DEBUG) printf("%s %d: " fmt, __FUNCTION__, __LINE__, ##args)
|
||||
#define debug_lev(lev, fmt, args...) \
|
||||
if (lev <= TSI108_ETH_DEBUG) \
|
||||
printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args)
|
||||
#else
|
||||
#define debug_lev(lev, fmt, args...) do{}while(0)
|
||||
#endif
|
||||
|
|
@ -658,9 +660,8 @@ static int marvell_88e_phy_config(struct eth_device *dev, int *speed,
|
|||
}
|
||||
} while ((phy_status & PHY_STAT_LINK_UP) == 0);
|
||||
|
||||
if ((phy_status & PHY_STAT_LINK_UP) == 0) {
|
||||
if ((phy_status & PHY_STAT_LINK_UP) == 0)
|
||||
return 0;
|
||||
}
|
||||
|
||||
value = 0;
|
||||
phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
|
||||
|
|
@ -681,10 +682,9 @@ static int marvell_88e_phy_config(struct eth_device *dev, int *speed,
|
|||
if (phy_spec_status & SPEC_STAT_FULL_DUP) {
|
||||
phy_duplex = LINK_DUPLEX_FULL;
|
||||
value |= PHY_CTRL_FULL_DUPLEX;
|
||||
} else {
|
||||
} else
|
||||
phy_duplex = LINK_DUPLEX_HALF;
|
||||
}
|
||||
}
|
||||
/* set TBI speed */
|
||||
write_phy (base, TBI_ADDR, PHY_CTRL_REG, value);
|
||||
write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060);
|
||||
|
|
@ -704,22 +704,19 @@ static int marvell_88e_phy_config(struct eth_device *dev, int *speed,
|
|||
printf (", 10 Mbps");
|
||||
break;
|
||||
}
|
||||
if (phy_duplex == LINK_DUPLEX_FULL) {
|
||||
if (phy_duplex == LINK_DUPLEX_FULL)
|
||||
printf (", Full duplex");
|
||||
} else {
|
||||
else
|
||||
printf (", Half duplex");
|
||||
}
|
||||
}
|
||||
printf ("\n");
|
||||
#endif
|
||||
|
||||
dump_phy_regs (TBI_ADDR);
|
||||
if (speed) {
|
||||
if (speed)
|
||||
*speed = phy_speed;
|
||||
}
|
||||
if (duplex) {
|
||||
if (duplex)
|
||||
*duplex = phy_duplex;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -794,25 +791,23 @@ static int tsi108_eth_probe(struct eth_device *dev, bd_t * bis)
|
|||
reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) |
|
||||
(dev->enetaddr[0] << 16);
|
||||
|
||||
if (marvell_88e_phy_config(dev, &speed, &duplex) == 0) {
|
||||
if (marvell_88e_phy_config(dev, &speed, &duplex) == 0)
|
||||
return 0;
|
||||
}
|
||||
|
||||
value =
|
||||
MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC |
|
||||
MAC_CONFIG_2_CRC_ENABLE;
|
||||
if (speed == LINK_SPEED_1000) {
|
||||
if (speed == LINK_SPEED_1000)
|
||||
value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_BYTE);
|
||||
} else {
|
||||
else {
|
||||
value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_NIBBLE);
|
||||
reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD;
|
||||
}
|
||||
if (duplex == LINK_DUPLEX_FULL) {
|
||||
value |= MAC_CONFIG_2_FULL_DUPLEX;
|
||||
reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT;
|
||||
} else {
|
||||
} else
|
||||
reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT;
|
||||
}
|
||||
reg_MAC_CONFIG_2(base) = value;
|
||||
|
||||
reg_RX_CONFIG(base) = RX_CONFIG_SE;
|
||||
|
|
@ -894,9 +889,8 @@ static int tsi108_eth_send(struct eth_device *dev,
|
|||
(unsigned long)tx_descr +
|
||||
sizeof(struct dma_descriptor));
|
||||
|
||||
if (timeout != 0) {
|
||||
if (timeout != 0)
|
||||
udelay (15);
|
||||
}
|
||||
if (++timeout > 10000) {
|
||||
tx_diag_regs(base);
|
||||
debug_lev(1,
|
||||
|
|
@ -1004,10 +998,9 @@ static int tsi108_eth_recv(struct eth_device *dev)
|
|||
rx_descr =
|
||||
(struct dma_descriptor
|
||||
*)(le32_to_cpu (rx_descr->next_descr_addr0));
|
||||
if (rx_descr == 0) {
|
||||
if (rx_descr == 0)
|
||||
rx_descr = &rx_descr_array[0];
|
||||
}
|
||||
}
|
||||
/* remember where we are for next time */
|
||||
rx_descr_current = rx_descr;
|
||||
|
||||
|
|
|
|||
|
|
@ -23,10 +23,9 @@
|
|||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_TSI108_I2C
|
||||
|
||||
#include <common.h>
|
||||
#include <tsi108.h>
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
|
||||
|
|
@ -58,16 +57,14 @@ static int i2c_read_byte(
|
|||
DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n",
|
||||
i2c_chan, chip_addr, byte_addr));
|
||||
|
||||
if (0 != i2c_chan) {
|
||||
if (0 != i2c_chan)
|
||||
chan_offset = TSI108_I2C_SDRAM_OFFSET;
|
||||
}
|
||||
|
||||
/* Check if I2C operation is in progress */
|
||||
temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
|
||||
|
||||
if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS |
|
||||
I2C_CNTRL2_START))
|
||||
) {
|
||||
I2C_CNTRL2_START))) {
|
||||
/* Set device address and operation (read = 0) */
|
||||
temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) |
|
||||
((chip_addr >> 3) & 0x0F);
|
||||
|
|
@ -141,7 +138,8 @@ static int i2c_read_byte(
|
|||
* Returns: 0 on success, not 0 on failure
|
||||
*/
|
||||
|
||||
int i2c_read(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, int len)
|
||||
int i2c_read (uchar chip_addr, uint byte_addr, int alen,
|
||||
uchar * buffer, int len)
|
||||
{
|
||||
u32 op_status = TSI108_I2C_PARAM_ERR;
|
||||
u32 i2c_if = 0;
|
||||
|
|
@ -210,7 +208,7 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */
|
|||
|
||||
/* Wait until operation completed */
|
||||
do {
|
||||
// Read I2C operation status
|
||||
/* Read I2C operation status */
|
||||
temp =
|
||||
*(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
|
||||
I2C_CNTRL2);
|
||||
|
|
|
|||
|
|
@ -24,12 +24,11 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/****************************************************************
|
||||
*
|
||||
/*
|
||||
* board specific configuration options for Freescale
|
||||
* MPC7448HPC2 (High-Performance Computing II) (Taiga) board
|
||||
*
|
||||
****************************************************************/
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
|
@ -99,8 +98,8 @@
|
|||
* for your console driver.
|
||||
*
|
||||
* what to do:
|
||||
* If you have hacked a serial cable onto the second DUART channel, change the CFG_DUART port from 1
|
||||
* to 0 below.
|
||||
* If you have hacked a serial cable onto the second DUART channel,
|
||||
* change the CFG_DUART port from 1 to 0 below.
|
||||
*
|
||||
*/
|
||||
|
||||
|
|
@ -118,7 +117,8 @@
|
|||
#define CONFIG_ZERO_BOOTDELAY_CHECK
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
|
||||
/* #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\"
|
||||
* to mount root filesystem over NFS;echo" */
|
||||
|
||||
#if (CONFIG_BOOTDELAY >= 0)
|
||||
#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\
|
||||
|
|
@ -211,8 +211,8 @@
|
|||
* CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
|
||||
* Environment variable 'test_dram_data' must be
|
||||
* set to 'y'.
|
||||
* CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word is uniquely
|
||||
* addressable. Environment variable
|
||||
* CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word
|
||||
* is uniquely addressable. Environment variable
|
||||
* 'test_dram_address' must be set to 'y'.
|
||||
* CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
|
||||
* This test takes about 6 minutes to test 64 MB.
|
||||
|
|
@ -286,9 +286,9 @@
|
|||
|
||||
/* Peripheral Device section */
|
||||
|
||||
/*******************************************************
|
||||
/*
|
||||
* Resources on the Tsi108
|
||||
*******************************************************/
|
||||
*/
|
||||
|
||||
#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */
|
||||
#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */
|
||||
|
|
@ -297,9 +297,9 @@
|
|||
|
||||
#undef DISABLE_PBM
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
|
|
@ -321,7 +321,7 @@
|
|||
|
||||
/* PCI Memory Space */
|
||||
#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS)
|
||||
#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) //CFG_PCI_MEM32_BASE = 0xE0000000
|
||||
#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) /* 0xE0000000 */
|
||||
#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */
|
||||
|
||||
/* PCI I/O Space */
|
||||
|
|
|
|||
|
|
@ -205,8 +205,8 @@
|
|||
/* I2C_TX_DATA : Unused/Reserved bits Definition */
|
||||
#define I2C_TX_DATA_RESERVED (0x00000000)
|
||||
|
||||
#define TSI108_I2C_OFFSET 0x7000 /* register block offset for general use I2C channel */
|
||||
#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* register block offset for SPD I2C channel */
|
||||
#define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */
|
||||
#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */
|
||||
|
||||
#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue