x86: Use Cache-As-RAM for initial stack
This commit is contained in:
Graeme Russ
parent
2e2613d2c4
commit
ed4cba79d6
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@ -37,6 +37,7 @@ COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o
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COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o
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SOBJS-$(CONFIG_SYS_SC520) += sc520_asm.o
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SOBJS-$(CONFIG_SYS_SC520) += sc520_car.o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
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@ -515,7 +515,7 @@ bad_ram:
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dram_done:
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/* Restore Boot Flags */
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movl %ebx, %ebp
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jmp mem_init_ret
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ret
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#if CONFIG_SYS_SDRAM_ECC_ENABLE
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.globl init_ecc
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@ -560,7 +560,7 @@ set_ecc:
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movb %al,(%edi)
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out:
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jmp init_ecc_ret
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ret
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#endif
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/*
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@ -605,4 +605,4 @@ bank3: movl (%edi), %eax
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done:
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movl %edx, %eax
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jmp get_mem_size_ret
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ret
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@ -0,0 +1,94 @@
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/*
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* (C) Copyright 2010
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* Graeme Russ <graeme.russ@gmail.com>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/processor-flags.h>
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#include <asm/ic/sc520.h>
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.section .text
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.globl car_init
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car_init:
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/*
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* How to enable Cache-As-RAM for the AMD Elan SC520:
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* 1. Turn off the CPU Cache (may not be strictly required)
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* 2. Set code execution PAR (usually the BOOTCS region) to be
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* non-cachable
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* 3. Create a Cachable PAR Region for an area of memory which is
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* a) NOT where the code is being executed
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* b) NOT SDRAM (Controller not initialised yet)
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* c) WILL response to read requests
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* The easiest way to do this is to create a second BOOTCS
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* PAR mappnig with an address != the PAR in step 2
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* 4. Issue a wbinvd to invalidate the CPU cache
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* 5. Turn on the CPU Cache
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* 6. Read 16kB from the cached PAR region setup in step 3
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* 7. Turn off the CPU Cache (but DO NOT issue a wbinvd)
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*
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* The following code uses PAR2 as the cached PAR (PAR0 and PAR1
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* are avoided as these are the only two PARs which can be used
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* as PCI BUS Memory regions which the board might require)
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*
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* The configuration of PAR2 must be set in the board configuration
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* file as CONFIG_SYS_SC520_CAR_PAR
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*/
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/* Configure Cache-As-RAM PAR */
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movl $CONFIG_SYS_SC520_CAR_PAR, %eax
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movl $SC520_PAR2, %edi
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movl %eax, (%edi)
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/* Trash the cache then turn it on */
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wbinvd
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movl %cr0, %eax
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andl $~(X86_CR0_NW | X86_CR0_CD), %eax
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movl %eax, %cr0
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/*
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* The cache is now enabled and empty. Map a region of memory to
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* it by reading that region.
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*/
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movl $CONFIG_SYS_CAR_ADDR, %esi
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movl $CONFIG_SYS_CAR_SIZE, %ecx
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shrl $2, %ecx /* we are reading longs */
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cld
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rep lodsl
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/* Turn off the cache, but don't trash it */
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movl %cr0, %eax
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orl $(X86_CR0_NW | X86_CR0_CD), %eax
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movl %eax, %cr0
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/* Clear the CAR region */
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xorl %eax, %eax
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movl $CONFIG_SYS_CAR_ADDR, %edi
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movl $CONFIG_SYS_CAR_SIZE, %ecx
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shrl $2, %ecx /* we are writing longs */
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rep stosl
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/*
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* Done - We should now have CONFIG_SYS_CAR_SIZE bytes of
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* Cache-As-RAM
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*/
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jmp car_init_ret
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@ -72,41 +72,40 @@ _start:
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.globl early_board_init_ret
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early_board_init_ret:
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/* Initialise Cache-As-RAM */
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jmp car_init
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.globl car_init_ret
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car_init_ret:
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/*
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* We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM,
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* or fully initialised SDRAM - we really don't care which)
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* starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack
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*/
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movl $CONFIG_SYS_INIT_SP_ADDR, %esp
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/* Skip memory initialization if not starting from cold-reset */
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movl %ebx, %ecx
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andl $GD_FLG_COLD_BOOT, %ecx
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jz skip_mem_init
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/* size memory */
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jmp mem_init
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.globl mem_init_ret
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mem_init_ret:
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call mem_init
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skip_mem_init:
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/* fetch memory size (into %eax) */
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jmp get_mem_size
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.globl get_mem_size_ret
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get_mem_size_ret:
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call get_mem_size
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movl %eax, %esp
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#if CONFIG_SYS_SDRAM_ECC_ENABLE
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/* Skip ECC initialization if not starting from cold-reset */
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movl %ebx, %ecx
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andl $GD_FLG_COLD_BOOT, %ecx
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jz init_ecc_ret
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jmp init_ecc
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jz skip_ecc_init
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call init_ecc
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.globl init_ecc_ret
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init_ecc_ret:
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skip_init_ecc:
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#endif
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/* Check we have enough memory for stack */
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movl $CONFIG_SYS_STACK_SIZE, %ecx
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cmpl %ecx, %eax
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jb die
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mem_ok:
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/* Set stack pointer to upper memory limit*/
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movl %eax, %esp
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/* Test the stack */
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pushl $0
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popl %ecx
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@ -161,6 +161,10 @@
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* 256kB Monitor
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*/
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#define CONFIG_SYS_STACK_SIZE 0x8000
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#define CONFIG_SYS_CAR_ADDR 0x19200000
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#define CONFIG_SYS_CAR_SIZE 0x00004000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_CAR_ADDR + \
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CONFIG_SYS_CAR_SIZE)
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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@ -478,6 +482,22 @@
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*/
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#define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800
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/*-----------------------------------------------------------------------
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* Cache-As-RAM (Targets Boot Flash)
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*
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* 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
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* \ / | | | | \--+--/ \-------+--------/
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* | | | | | | +------------ Start at 0x19200000
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* | | | | | +------------------------- 64k Region Size
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* | | | | | ((15 + 1) * 4kB)
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* | | | | +------------------------------ 4kB Page Size
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* | | | +-------------------------------- Writes Enabled
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* | | +---------------------------------- Caching Enabled
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* | +------------------------------------ Execution Prevented
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* +--------------------------------------- BOOTCS
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*/
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#define CONFIG_SYS_SC520_CAR_PAR 0x903d9200
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/*-----------------------------------------------------------------------
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* PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
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*
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