stm32f4: Add support for stm32f429-discovery board

Signed-off-by: Kamil Lulko <rev13@wp.pl>
Reviewed-by: Tom Rini <trini@konsulko.com>

arch/arm/Kconfig

@@ -789,6 +789,10 @@ config ARCH_UNIPHIER
 	select DM_SERIAL
 	select DM_I2C
 
+config TARGET_STM32F429_DISCOVERY
+	bool "Support STM32F429 Discovery"
+	select CPU_V7M
+
 endchoice
 
 source "arch/arm/mach-at91/Kconfig"
@@ -926,6 +930,7 @@ source "board/spear/spear600/Kconfig"
 source "board/spear/x600/Kconfig"
 source "board/st-ericsson/snowball/Kconfig"
 source "board/st-ericsson/u8500/Kconfig"
+source "board/st/stm32f429-discovery/Kconfig"
 source "board/st/stv0991/Kconfig"
 source "board/sunxi/Kconfig"
 source "board/syteco/zmx25/Kconfig"

board/st/stm32f429-discovery/Kconfig

@@ -0,0 +1,19 @@
+if TARGET_STM32F429_DISCOVERY
+
+config SYS_BOARD
+	string
+	default "stm32f429-discovery"
+
+config SYS_VENDOR
+	string
+	default "st"
+
+config SYS_SOC
+	string
+	default "stm32f4"
+
+config SYS_CONFIG_NAME
+	string
+	default "stm32f429-discovery"
+
+endif

board/st/stm32f429-discovery/MAINTAINERS

@@ -0,0 +1,5 @@
+M:	Kamil Lulko <rev13@wp.pl>
+S:	Maintained
+F:	board/st/stm32f429-discovery/
+F:	include/configs/stm32f429-discovery.h
+F:	configs/stm32f429-discovery_defconfig

board/st/stm32f429-discovery/Makefile

@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2015
+# Kamil Lulko, <rev13@wp.pl>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= stm32f429-discovery.o
+obj-y	+= led.o

board/st/stm32f429-discovery/led.c

@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm-generic/gpio.h>
+
+void coloured_LED_init(void)
+{
+	gpio_direction_output(CONFIG_RED_LED, 0);
+	gpio_direction_output(CONFIG_GREEN_LED, 0);
+}
+
+void red_led_off(void)
+{
+	gpio_set_value(CONFIG_RED_LED, 0);
+}
+
+void green_led_off(void)
+{
+	gpio_set_value(CONFIG_GREEN_LED, 0);
+}
+
+void red_led_on(void)
+{
+	gpio_set_value(CONFIG_RED_LED, 1);
+}
+
+void green_led_on(void)
+{
+	gpio_set_value(CONFIG_GREEN_LED, 1);
+}

board/st/stm32f429-discovery/stm32f429-discovery.c

@@ -0,0 +1,287 @@
+/*
+ * (C) Copyright 2011, 2012, 2013
+ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
+ * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
+ * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
+ * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/fmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct stm32_gpio_ctl gpio_ctl_gpout = {
+	.mode = STM32_GPIO_MODE_OUT,
+	.otype = STM32_GPIO_OTYPE_PP,
+	.speed = STM32_GPIO_SPEED_50M,
+	.pupd = STM32_GPIO_PUPD_NO,
+	.af = STM32_GPIO_AF0
+};
+
+const struct stm32_gpio_ctl gpio_ctl_usart = {
+	.mode = STM32_GPIO_MODE_AF,
+	.otype = STM32_GPIO_OTYPE_PP,
+	.speed = STM32_GPIO_SPEED_50M,
+	.pupd = STM32_GPIO_PUPD_UP,
+	.af = STM32_GPIO_AF7
+};
+
+static const struct stm32_gpio_dsc usart1_gpio[] = {
+	{STM32_GPIO_PORT_A, STM32_GPIO_PIN_9},	/* TX */
+	{STM32_GPIO_PORT_A, STM32_GPIO_PIN_10},	/* RX */
+};
+
+int uart1_setup_gpio(void)
+{
+	int i;
+	int rv = 0;
+
+	for (i = 0; i < ARRAY_SIZE(usart1_gpio); i++) {
+		rv = stm32_gpio_config(&usart1_gpio[i], &gpio_ctl_usart);
+		if (rv)
+			goto out;
+	}
+
+out:
+	return rv;
+}
+
+const struct stm32_gpio_ctl gpio_ctl_fmc = {
+	.mode = STM32_GPIO_MODE_AF,
+	.otype = STM32_GPIO_OTYPE_PP,
+	.speed = STM32_GPIO_SPEED_100M,
+	.pupd = STM32_GPIO_PUPD_NO,
+	.af = STM32_GPIO_AF12
+};
+
+static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = {
+	/* Chip is LQFP144, see DM00077036.pdf for details */
+	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_10},	/* 79, FMC_D15 */
+	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_9},	/* 78, FMC_D14 */
+	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_8},	/* 77, FMC_D13 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_15},	/* 68, FMC_D12 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_14},	/* 67, FMC_D11 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_13},	/* 66, FMC_D10 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_12},	/* 65, FMC_D9 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_11},	/* 64, FMC_D8 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_10},	/* 63, FMC_D7 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_9},	/* 60, FMC_D6 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_8},	/* 59, FMC_D5 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_7},	/* 58, FMC_D4 */
+	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_1},	/* 115, FMC_D3 */
+	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_0},	/* 114, FMC_D2 */
+	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_15},	/* 86, FMC_D1 */
+	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_14},	/* 85, FMC_D0 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_1},	/* 142, FMC_NBL1 */
+	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_0},	/* 141, FMC_NBL0 */
+	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_5},	/* 90, FMC_A15, BA1 */
+	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_4},	/* 89, FMC_A14, BA0 */
+	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_1},	/* 57, FMC_A11 */
+	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_0},	/* 56, FMC_A10 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_15},	/* 55, FMC_A9 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_14},	/* 54, FMC_A8 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_13},	/* 53, FMC_A7 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_12},	/* 50, FMC_A6 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_5},	/* 15, FMC_A5 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_4},	/* 14, FMC_A4 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_3},	/* 13, FMC_A3 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_2},	/* 12, FMC_A2 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_1},	/* 11, FMC_A1 */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_0},	/* 10, FMC_A0 */
+	{STM32_GPIO_PORT_B, STM32_GPIO_PIN_6},	/* 136, SDRAM_NE */
+	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_11},	/* 49, SDRAM_NRAS */
+	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_15},	/* 132, SDRAM_NCAS */
+	{STM32_GPIO_PORT_C, STM32_GPIO_PIN_0},	/* 26, SDRAM_NWE */
+	{STM32_GPIO_PORT_B, STM32_GPIO_PIN_5},	/* 135, SDRAM_CKE */
+	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_8},	/* 93, SDRAM_CLK */
+};
+
+static int fmc_setup_gpio(void)
+{
+	int rv = 0;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
+		rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
+				&gpio_ctl_fmc);
+		if (rv)
+			goto out;
+	}
+
+out:
+	return rv;
+}
+
+/*
+ * STM32 RCC FMC specific definitions
+ */
+#define STM32_RCC_ENR_FMC	(1 << 0)	/* FMC module clock  */
+
+static inline u32 _ns2clk(u32 ns, u32 freq)
+{
+	u32 tmp = freq/1000000;
+	return (tmp * ns) / 1000;
+}
+
+#define NS2CLK(ns) (_ns2clk(ns, freq))
+
+/*
+ * Following are timings for IS42S16400J, from corresponding datasheet
+ */
+#define SDRAM_CAS	3	/* 3 cycles */
+#define SDRAM_NB	1	/* Number of banks */
+#define SDRAM_MWID	1	/* 16 bit memory */
+
+#define SDRAM_NR	0x1	/* 12-bit row */
+#define SDRAM_NC	0x0	/* 8-bit col */
+#define SDRAM_RBURST	0x1	/* Single read requests always as bursts */
+#define SDRAM_RPIPE	0x0	/* No HCLK clock cycle delay */
+
+#define SDRAM_TRRD	(NS2CLK(14) - 1)
+#define SDRAM_TRCD	(NS2CLK(15) - 1)
+#define SDRAM_TRP	(NS2CLK(15) - 1)
+#define SDRAM_TRAS	(NS2CLK(42) - 1)
+#define SDRAM_TRC	(NS2CLK(63) - 1)
+#define SDRAM_TRFC	(NS2CLK(63) - 1)
+#define SDRAM_TCDL	(1 - 1)
+#define SDRAM_TRDL	(2 - 1)
+#define SDRAM_TBDL	(1 - 1)
+#define SDRAM_TREF	1386
+#define SDRAM_TCCD	(1 - 1)
+
+#define SDRAM_TXSR	(NS2CLK(70) - 1)/* Row cycle time after precharge */
+#define SDRAM_TMRD	(3 - 1)		/* Page 10, Mode Register Set */
+
+/* Last data-in to row precharge, need also comply ineq from RM 37.7.5 */
+#define SDRAM_TWR	max(\
+	(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD - 1)), \
+	(int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP - 2)\
+)
+
+#define SDRAM_MODE_BL_SHIFT	0
+#define SDRAM_MODE_CAS_SHIFT	4
+#define SDRAM_MODE_BL		0
+#define SDRAM_MODE_CAS		SDRAM_CAS
+
+int dram_init(void)
+{
+	u32 freq;
+	int rv;
+
+	rv = fmc_setup_gpio();
+	if (rv)
+		return rv;
+
+	setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC);
+
+	/*
+	 * Get frequency for NS2CLK calculation.
+	 */
+	freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
+
+	writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
+		| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
+		| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
+		&STM32_SDRAM_FMC->sdcr1);
+
+	writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
+		| SDRAM_CAS << FMC_SDCR_CAS_SHIFT
+		| SDRAM_NB << FMC_SDCR_NB_SHIFT
+		| SDRAM_MWID << FMC_SDCR_MWID_SHIFT
+		| SDRAM_NR << FMC_SDCR_NR_SHIFT
+		| SDRAM_NC << FMC_SDCR_NC_SHIFT
+		| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
+		| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
+		&STM32_SDRAM_FMC->sdcr2);
+
+	writel(SDRAM_TRP << FMC_SDTR_TRP_SHIFT
+		| SDRAM_TRC << FMC_SDTR_TRC_SHIFT,
+		&STM32_SDRAM_FMC->sdtr1);
+
+	writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
+		| SDRAM_TRP << FMC_SDTR_TRP_SHIFT
+		| SDRAM_TWR << FMC_SDTR_TWR_SHIFT
+		| SDRAM_TRC << FMC_SDTR_TRC_SHIFT
+		| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
+		| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
+		| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
+		&STM32_SDRAM_FMC->sdtr2);
+
+	writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK,
+	       &STM32_SDRAM_FMC->sdcmr);
+
+	udelay(200);	/* 200 us delay, page 10, "Power-Up" */
+	FMC_BUSY_WAIT();
+
+	writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE,
+	       &STM32_SDRAM_FMC->sdcmr);
+
+	udelay(100);
+	FMC_BUSY_WAIT();
+
+	writel((FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH
+		| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
+
+	udelay(100);
+	FMC_BUSY_WAIT();
+
+	writel(FMC_SDCMR_BANK_2 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
+		| SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
+		<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
+		&STM32_SDRAM_FMC->sdcmr);
+
+	udelay(100);
+
+	FMC_BUSY_WAIT();
+
+	writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL,
+	       &STM32_SDRAM_FMC->sdcmr);
+
+	FMC_BUSY_WAIT();
+
+	/* Refresh timer */
+	writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
+
+	/*
+	 * Fill in global info with description of SRAM configuration
+	 */
+	gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
+	gd->bd->bi_dram[0].size  = CONFIG_SYS_RAM_SIZE;
+
+	gd->ram_size = CONFIG_SYS_RAM_SIZE;
+
+	return rv;
+}
+
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	int res;
+
+	res = uart1_setup_gpio();
+	if (res)
+		return res;
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}

configs/stm32f429-discovery_defconfig

@@ -0,0 +1,2 @@
+CONFIG_ARM=y
+CONFIG_TARGET_STM32F429_DISCOVERY=y

include/configs/stm32f429-discovery.h

@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_STM32F4
+#define CONFIG_STM32F4DISCOVERY
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_FLASH_BASE		0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x10010000
+#define CONFIG_SYS_TEXT_BASE		0x08000000
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_RAM_SIZE		(8 << 20)
+#define CONFIG_SYS_RAM_CS		1
+#define CONFIG_SYS_RAM_FREQ_DIV		2
+#define CONFIG_SYS_RAM_BASE		0xD0000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_RAM_BASE
+#define CONFIG_SYS_LOAD_ADDR		0xD0400000
+#define CONFIG_LOADADDR			0xD0400000
+
+#define CONFIG_SYS_MAX_FLASH_SECT	12
+#define CONFIG_SYS_MAX_FLASH_BANKS	2
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET		(256 << 10)
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)
+#define CONFIG_ENV_SIZE			(8 << 10)
+
+#define CONFIG_BOARD_SPECIFIC_LED
+#define CONFIG_RED_LED			110
+#define CONFIG_GREEN_LED		109
+
+#define CONFIG_STM32_GPIO
+#define CONFIG_STM32_SERIAL
+
+#define CONFIG_STM32_USART1
+
+#define CONFIG_STM32_HSE_HZ		8000000
+
+#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_SYS_MAXARGS		16
+
+#define CONFIG_SYS_MALLOC_LEN		(2 << 20)
+
+#define CONFIG_STACKSIZE		(64 << 10)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"console=ttystm0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+#define CONFIG_BOOTCOMMAND						\
+	"run bootcmd_romfs"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
+	"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
+	"bootm 0x08044000 - 0x08042000\0"
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_AUTOBOOT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT	       "U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MEM
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_TIMER
+
+#endif /* __CONFIG_H */