Add support for Freescale's mx35pdk board.
The patch adds suupport for the Freescale's mx35pdk board (known as well as mx35_3stack). The board boots from the NOR flash. Following devices are supported: - two ethernet devices (FEC and SMC911x on debug board) - I2C - PMIC (MC13892) via I2C interface - UART - NOR flash (64MB) - NAND flash (2GB) - basic access to mc9sdz60 registers via I2C interface Signed-off-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Stefano Babic
Albert Aribaud
parent
ac87c17d34
commit
eae4988b45
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@ -557,9 +557,10 @@ Rowel Atienza <rowel@diwalabs.com>
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Stefano Babic <sbabic@denx.de>
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ea20 davinci
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mx35pdk i.MX35
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mx51evk i.MX51
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polaris xscale
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trizepsiv xscale
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mx51evk i.MX51
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vision2 i.MX51
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Jason Liu <r64343@freescale.com>
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@ -0,0 +1,49 @@
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#
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# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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#
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# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := mx35pdk.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,363 @@
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/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/asm-offsets.h>
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#include "mx35pdk.h"
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/*
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* return soc version
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* 0x10: TO1
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* 0x20: TO2
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* 0x30: TO3
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*/
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.macro check_soc_version ret, tmp
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ldr \tmp, =IIM_BASE_ADDR
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ldr \ret, [\tmp, #IIM_SREV]
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cmp \ret, #0x00
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moveq \tmp, #ROMPATCH_REV
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ldreq \ret, [\tmp]
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moveq \ret, \ret, lsl #4
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addne \ret, \ret, #0x10
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.endm
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/*
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* AIPS setup - Only setup MPROTx registers.
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* The PACR default values are good.
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*/
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.macro init_aips
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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ldr r0, =AIPS1_BASE_ADDR
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ldr r1, =AIPS_MPR_CONFIG
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str r1, [r0, #0x00]
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str r1, [r0, #0x04]
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ldr r0, =AIPS2_BASE_ADDR
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str r1, [r0, #0x00]
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str r1, [r0, #0x04]
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/*
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* Clear the on and off peripheral modules Supervisor Protect bit
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* for SDMA to access them. Did not change the AIPS control registers
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* (offset 0x20) access type
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*/
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ldr r0, =AIPS1_BASE_ADDR
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ldr r1, =AIPS_OPACR_CONFIG
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str r1, [r0, #0x40]
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str r1, [r0, #0x44]
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str r1, [r0, #0x48]
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str r1, [r0, #0x4C]
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str r1, [r0, #0x50]
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ldr r0, =AIPS2_BASE_ADDR
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str r1, [r0, #0x40]
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str r1, [r0, #0x44]
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str r1, [r0, #0x48]
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str r1, [r0, #0x4C]
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str r1, [r0, #0x50]
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.endm
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/* MAX (Multi-Layer AHB Crossbar Switch) setup */
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.macro init_max
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ldr r0, =MAX_BASE_ADDR
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/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
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ldr r1, =MAX_MPR_CONFIG
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str r1, [r0, #0x000] /* for S0 */
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str r1, [r0, #0x100] /* for S1 */
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str r1, [r0, #0x200] /* for S2 */
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str r1, [r0, #0x300] /* for S3 */
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str r1, [r0, #0x400] /* for S4 */
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/* SGPCR - always park on last master */
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ldr r1, =MAX_SGPCR_CONFIG
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str r1, [r0, #0x010] /* for S0 */
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str r1, [r0, #0x110] /* for S1 */
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str r1, [r0, #0x210] /* for S2 */
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str r1, [r0, #0x310] /* for S3 */
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str r1, [r0, #0x410] /* for S4 */
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/* MGPCR - restore default values */
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ldr r1, =MAX_MGPCR_CONFIG
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str r1, [r0, #0x800] /* for M0 */
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str r1, [r0, #0x900] /* for M1 */
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str r1, [r0, #0xA00] /* for M2 */
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str r1, [r0, #0xB00] /* for M3 */
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str r1, [r0, #0xC00] /* for M4 */
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str r1, [r0, #0xD00] /* for M5 */
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.endm
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/* M3IF setup */
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.macro init_m3if
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/* Configure M3IF registers */
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ldr r1, =M3IF_BASE_ADDR
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/*
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* M3IF Control Register (M3IFCTL)
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* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
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* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
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* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
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* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
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* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
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* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
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* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
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* ------------
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* 0x00000040
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*/
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ldr r0, =M3IF_CONFIG
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str r0, [r1] /* M3IF control reg */
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.endm
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/* CPLD on CS5 setup */
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.macro init_debug_board
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ldr r0, =DBG_BASE_ADDR
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ldr r1, =DBG_CSCR_U_CONFIG
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str r1, [r0, #0x00]
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ldr r1, =DBG_CSCR_L_CONFIG
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str r1, [r0, #0x04]
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ldr r1, =DBG_CSCR_A_CONFIG
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str r1, [r0, #0x08]
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.endm
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/* clock setup */
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.macro init_clock
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ldr r0, =CCM_BASE_ADDR
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/* default CLKO to 1/32 of the ARM core*/
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ldr r1, [r0, #CLKCTL_COSR]
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bic r1, r1, #0x00000FF00
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bic r1, r1, #0x0000000FF
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mov r2, #0x00006C00
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add r2, r2, #0x67
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orr r1, r1, r2
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str r1, [r0, #CLKCTL_COSR]
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ldr r2, =CCM_CCMR_CONFIG
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str r2, [r0, #CLKCTL_CCMR]
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check_soc_version r1, r2
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cmp r1, #CHIP_REV_2_0
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ldrhs r3, =CCM_MPLL_532_HZ
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bhs 1f
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ldr r2, [r0, #CLKCTL_PDR0]
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tst r2, #CLKMODE_CONSUMER
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ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
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ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
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1:
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str r3, [r0, #CLKCTL_MPCTL]
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ldr r1, =CCM_PPLL_300_HZ
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str r1, [r0, #CLKCTL_PPCTL]
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ldr r1, =CCM_PDR0_CONFIG
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bic r1, r1, #0x800000
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str r1, [r0, #CLKCTL_PDR0]
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ldr r1, [r0, #CLKCTL_CGR0]
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orr r1, r1, #0x0C300000
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str r1, [r0, #CLKCTL_CGR0]
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ldr r1, [r0, #CLKCTL_CGR1]
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orr r1, r1, #0x00000C00
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orr r1, r1, #0x00000003
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str r1, [r0, #CLKCTL_CGR1]
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.endm
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.macro setup_sdram
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ldr r0, =ESDCTL_BASE_ADDR
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mov r3, #0x2000
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str r3, [r0, #0x0]
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str r3, [r0, #0x8]
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/*ip(r12) has used to save lr register in upper calling*/
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mov fp, lr
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mov r5, #0x00
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mov r2, #0x00
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mov r1, #CSD0_BASE_ADDR
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bl setup_sdram_bank
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cmp r3, #0x0
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orreq r5, r5, #1
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eorne r2, r2, #0x1
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blne setup_sdram_bank
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mov lr, fp
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1:
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ldr r3, =ESDCTL_DELAY_LINE5
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str r3, [r0, #0x30]
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.endm
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.globl lowlevel_init
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lowlevel_init:
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mov r10, lr
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mrc 15, 0, r1, c1, c0, 0
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mrc 15, 0, r0, c1, c0, 1
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orr r0, r0, #7
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mcr 15, 0, r0, c1, c0, 1
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orr r1, r1, #(1<<11)
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/* Set unaligned access enable */
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orr r1, r1, #(1<<22)
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/* Set low int latency enable */
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orr r1, r1, #(1<<21)
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mcr 15, 0, r1, c1, c0, 0
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mov r0, #0
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/* Set branch prediction enable */
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mcr 15, 0, r0, c15, c2, 4
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mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
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mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
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mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
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/*
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* initializes very early AIPS
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* Then it also initializes Multi-Layer AHB Crossbar Switch,
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* M3IF
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* Also setup the Peripheral Port Remap register inside the core
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*/
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ldr r0, =0x40000015 /* start from AIPS 2GB region */
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mcr p15, 0, r0, c15, c2, 4
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init_aips
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init_max
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init_m3if
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init_clock
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init_debug_board
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cmp pc, #PHYS_SDRAM_1
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blo init_sdram_start
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cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
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blo skip_sdram_setup
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init_sdram_start:
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/*init_sdram*/
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setup_sdram
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skip_sdram_setup:
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mov lr, r10
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mov pc, lr
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/*
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* r0: ESDCTL control base, r1: sdram slot base
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* r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
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*/
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setup_sdram_bank:
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mov r3, #0xE
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tst r2, #0x1
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orreq r3, r3, #0x300 /*DDR2*/
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str r3, [r0, #0x10]
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bic r3, r3, #0x00A
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str r3, [r0, #0x10]
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beq 2f
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mov r3, #0x20000
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1: subs r3, r3, #1
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bne 1b
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2: tst r2, #0x1
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ldreq r3, =ESDCTL_DDR2_CONFIG
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ldrne r3, =ESDCTL_MDDR_CONFIG
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cmp r1, #CSD1_BASE_ADDR
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strlo r3, [r0, #0x4]
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strhs r3, [r0, #0xC]
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ldr r3, =ESDCTL_0x92220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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ldr r4, =ESDCTL_PRECHARGE
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strb r3, [r1, r4]
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tst r2, #0x1
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bne skip_set_mode
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cmp r1, #CSD1_BASE_ADDR
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ldr r3, =ESDCTL_0xB2220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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ldr r4, =ESDCTL_DDR2_EMR2
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strb r3, [r1, r4]
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ldr r4, =ESDCTL_DDR2_EMR3
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strb r3, [r1, r4]
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ldr r4, =ESDCTL_DDR2_EN_DLL
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strb r3, [r1, r4]
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ldr r4, =ESDCTL_DDR2_RESET_DLL
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strb r3, [r1, r4]
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ldr r3, =ESDCTL_0x92220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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ldr r4, =ESDCTL_PRECHARGE
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strb r3, [r1, r4]
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skip_set_mode:
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cmp r1, #CSD1_BASE_ADDR
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ldr r3, =ESDCTL_0xA2220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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strb r3, [r1]
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strb r3, [r1]
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ldr r3, =ESDCTL_0xB2220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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tst r2, #0x1
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ldreq r4, =ESDCTL_DDR2_MR
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ldrne r4, =ESDCTL_MDDR_MR
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mov r3, #0xDA
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strb r3, [r1, r4]
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ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
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streqb r3, [r1, r4]
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ldreq r4, =ESDCTL_DDR2_EN_DLL
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ldrne r4, =ESDCTL_MDDR_EMR
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strb r3, [r1, r4]
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cmp r1, #CSD1_BASE_ADDR
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ldr r3, =ESDCTL_0x82228080
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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tst r2, #0x1
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moveq r4, #0x20000
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movne r4, #0x200
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1: subs r4, r4, #1
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bne 1b
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str r3, [r1, #0x100]
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ldr r4, [r1, #0x100]
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cmp r3, r4
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movne r3, #1
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moveq r3, #0
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mov pc, lr
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@ -0,0 +1,297 @@
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/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/mx35_pins.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <i2c.h>
|
||||
#include <fsl_pmic.h>
|
||||
#include <mc9sdz60.h>
|
||||
#include <mc13892.h>
|
||||
#include <linux/types.h>
|
||||
#include <mxc_gpio.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <netdev.h>
|
||||
|
||||
#ifndef BOARD_LATE_INIT
|
||||
#error "BOARD_LATE_INIT must be set for this board"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_BOARD_EARLY_INIT_F
|
||||
#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
|
||||
#endif
|
||||
|
||||
#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
|
||||
PHYS_SDRAM_1_SIZE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void setup_iomux_i2c(void)
|
||||
{
|
||||
int pad;
|
||||
|
||||
/* setup pins for I2C1 */
|
||||
mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
|
||||
|
||||
pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
|
||||
| PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
|
||||
|
||||
mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
|
||||
mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
|
||||
}
|
||||
|
||||
|
||||
static void setup_iomux_spi(void)
|
||||
{
|
||||
mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
|
||||
}
|
||||
|
||||
static void setup_iomux_fec(void)
|
||||
{
|
||||
int pad;
|
||||
|
||||
/* setup pins for FEC */
|
||||
mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
|
||||
mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
|
||||
|
||||
pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \
|
||||
PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW);
|
||||
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \
|
||||
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \
|
||||
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \
|
||||
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \
|
||||
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \
|
||||
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \
|
||||
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \
|
||||
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
struct ccm_regs *ccm =
|
||||
(struct ccm_regs *)IMX_CCM_BASE;
|
||||
|
||||
/* enable clocks */
|
||||
writel(readl(&ccm->cgr0) |
|
||||
MXC_CCM_CGR0_EMI_MASK |
|
||||
MXC_CCM_CGR0_EDI0_MASK |
|
||||
MXC_CCM_CGR0_EPIT1_MASK,
|
||||
&ccm->cgr0);
|
||||
|
||||
writel(readl(&ccm->cgr1) |
|
||||
MXC_CCM_CGR1_FEC_MASK |
|
||||
MXC_CCM_CGR1_GPIO1_MASK |
|
||||
MXC_CCM_CGR1_GPIO2_MASK |
|
||||
MXC_CCM_CGR1_GPIO3_MASK |
|
||||
MXC_CCM_CGR1_I2C1_MASK |
|
||||
MXC_CCM_CGR1_I2C2_MASK |
|
||||
MXC_CCM_CGR1_IPU_MASK,
|
||||
&ccm->cgr1);
|
||||
|
||||
/* Setup NAND */
|
||||
__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
|
||||
|
||||
setup_iomux_i2c();
|
||||
setup_iomux_fec();
|
||||
setup_iomux_spi();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int pmic_detect(void)
|
||||
{
|
||||
int id;
|
||||
|
||||
id = pmic_reg_read(REG_IDENTIFICATION);
|
||||
|
||||
id = (id >> 6) & 0x7;
|
||||
if (id == 0x7)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
int rev;
|
||||
|
||||
rev = pmic_detect();
|
||||
|
||||
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
u8 val;
|
||||
u32 pmic_val;
|
||||
|
||||
if (pmic_detect()) {
|
||||
mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
|
||||
MUX_CONFIG_ALT1);
|
||||
|
||||
pmic_val = pmic_reg_read(REG_SETTING_0);
|
||||
pmic_reg_write(REG_SETTING_0, pmic_val | VO_1_30V | VO_1_50V);
|
||||
pmic_val = pmic_reg_read(REG_MODE_0);
|
||||
pmic_reg_write(REG_MODE_0, pmic_val | VGEN3EN);
|
||||
|
||||
mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
|
||||
mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
|
||||
|
||||
mxc_gpio_direction(37, MXC_GPIO_DIRECTION_OUT);
|
||||
mxc_gpio_set(37, 1);
|
||||
}
|
||||
|
||||
val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
|
||||
mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
|
||||
mdelay(200);
|
||||
|
||||
val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
|
||||
mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
|
||||
mdelay(200);
|
||||
|
||||
val |= 0x80;
|
||||
mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
struct ccm_regs *ccm =
|
||||
(struct ccm_regs *)IMX_CCM_BASE;
|
||||
u32 cpu_rev = get_cpu_rev();
|
||||
|
||||
/*
|
||||
* Be sure that I2C is initialized to check
|
||||
* the board revision
|
||||
*/
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
|
||||
/* Print board revision */
|
||||
printf("Board: MX35 PDK %d.0 ", ((get_board_rev() >> 8) + 1) & 0x0F);
|
||||
|
||||
/* Print CPU revision */
|
||||
printf("i.MX35 %d.%d [", (cpu_rev & 0xF0) >> 4, cpu_rev & 0x0F);
|
||||
|
||||
switch (readl(&ccm->rcsr) & 0x0F) {
|
||||
case 0x0000:
|
||||
puts("POR");
|
||||
break;
|
||||
case 0x0002:
|
||||
puts("JTAG");
|
||||
break;
|
||||
case 0x0004:
|
||||
puts("RST");
|
||||
break;
|
||||
case 0x0008:
|
||||
puts("WDT");
|
||||
break;
|
||||
default:
|
||||
puts("unknown");
|
||||
}
|
||||
puts("]\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = -ENODEV;
|
||||
#if defined(CONFIG_SMC911X)
|
||||
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
|
||||
#endif
|
||||
|
||||
cpu_eth_init(bis);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
*
|
||||
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
|
||||
*
|
||||
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_MX35_3STACK_H
|
||||
#define __BOARD_MX35_3STACK_H
|
||||
|
||||
#define AIPS_MPR_CONFIG 0x77777777
|
||||
#define AIPS_OPACR_CONFIG 0x00000000
|
||||
|
||||
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
|
||||
#define MAX_MPR_CONFIG 0x00302154
|
||||
/* SGPCR - always park on last master */
|
||||
#define MAX_SGPCR_CONFIG 0x00000010
|
||||
/* MGPCR - restore default values */
|
||||
#define MAX_MGPCR_CONFIG 0x00000000
|
||||
|
||||
/*
|
||||
* M3IF Control Register (M3IFCTL)
|
||||
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
|
||||
* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
|
||||
* ------------
|
||||
* 0x00000040
|
||||
*/
|
||||
#define M3IF_CONFIG 0x00000040
|
||||
|
||||
#define DBG_BASE_ADDR WEIM_CTRL_CS5
|
||||
#define DBG_CSCR_U_CONFIG 0x0000D843
|
||||
#define DBG_CSCR_L_CONFIG 0x22252521
|
||||
#define DBG_CSCR_A_CONFIG 0x22220A00
|
||||
|
||||
#define CCM_CCMR_CONFIG 0x003F4208
|
||||
#define CCM_PDR0_CONFIG 0x00801000
|
||||
|
||||
#define PLL_BRM_OFFSET 31
|
||||
#define PLL_PD_OFFSET 26
|
||||
#define PLL_MFD_OFFSET 16
|
||||
#define PLL_MFI_OFFSET 10
|
||||
|
||||
#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET)
|
||||
#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET)
|
||||
#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET)
|
||||
#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET)
|
||||
#define _PLL_MFN(x) (x)
|
||||
#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
|
||||
(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
|
||||
_PLL_MFN(mfn))
|
||||
|
||||
#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1)
|
||||
#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
|
||||
#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
|
||||
|
||||
/* MEMORY SETTING */
|
||||
#define ESDCTL_0x92220000 0x92220000
|
||||
#define ESDCTL_0xA2220000 0xA2220000
|
||||
#define ESDCTL_0xB2220000 0xB2220000
|
||||
#define ESDCTL_0x82228080 0x82228080
|
||||
|
||||
#define ESDCTL_PRECHARGE 0x00000400
|
||||
|
||||
#define ESDCTL_MDDR_CONFIG 0x007FFC3F
|
||||
#define ESDCTL_MDDR_MR 0x00000033
|
||||
#define ESDCTL_MDDR_EMR 0x02000000
|
||||
|
||||
#define ESDCTL_DDR2_CONFIG 0x007FFC3F
|
||||
#define ESDCTL_DDR2_EMR2 0x04000000
|
||||
#define ESDCTL_DDR2_EMR3 0x06000000
|
||||
#define ESDCTL_DDR2_EN_DLL 0x02000400
|
||||
#define ESDCTL_DDR2_RESET_DLL 0x00000333
|
||||
#define ESDCTL_DDR2_MR 0x00000233
|
||||
#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
|
||||
|
||||
#define ESDCTL_DELAY_LINE5 0x00F49F00
|
||||
#endif /* __BOARD_MX35_3STACK_H */
|
||||
|
|
@ -38,6 +38,7 @@
|
|||
qong arm arm1136 - davedenx mx31
|
||||
mx31ads arm arm1136 - freescale mx31
|
||||
imx31_litekit arm arm1136 - logicpd mx31
|
||||
mx35pdk arm arm1136 - freescale mx35
|
||||
omap2420h4 arm arm1136 - ti omap24xx
|
||||
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
|
||||
armadillo arm arm720t
|
||||
|
|
|
|||
|
|
@ -0,0 +1,188 @@
|
|||
Overview
|
||||
--------------
|
||||
|
||||
mx35pdk (known als as mx35_3stack) is a development board by Freescale.
|
||||
It consists of three pluggable board:
|
||||
- CPU module, with CPU, RAM, flash
|
||||
- Personality board, with most interfaces (USB, Network,..)
|
||||
- Debug board with JTAG header.
|
||||
|
||||
The board is usually delivered with redboot. This howto explains how to boot
|
||||
a linux kernel and how to replace the original bootloader with U-Boot.
|
||||
|
||||
The board is delivered with Redboot on the NAND flash. It is possible to
|
||||
switch the boot device with the switches SW1-SW2 on the Personality board,
|
||||
and with SW5-SW10 on the Debug board.
|
||||
|
||||
Delivered Redboot script to start the kernel
|
||||
---------------------------------------------------
|
||||
|
||||
In redboot the following script is stored:
|
||||
|
||||
fis load kernel
|
||||
exec -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock8 rw rootfstype=jffs2 ip=dhcp fec_mac=00:04:9F:00:E7:76"
|
||||
|
||||
Kernel is taken from flash. The image is in zImage format.
|
||||
|
||||
Booting from NET, rootfs on NFS:
|
||||
-----------------------------------
|
||||
|
||||
To change the script in redboot:
|
||||
|
||||
load -r -b 0x100000 <path_to_zImage>
|
||||
exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/armVFP rw ip=dhcp"
|
||||
|
||||
If the ip address is not set, you can set it with :
|
||||
|
||||
ip_address -l <board_ip/netmask> -h <server_ip>
|
||||
|
||||
Linux partitions:
|
||||
---------------------------
|
||||
|
||||
As default, the board is shipped with these partition tables for NAND
|
||||
and for NOR:
|
||||
|
||||
Creating 5 MTD partitions on "NAND 2GiB 3,3V 8-bit":
|
||||
0x00000000-0x00100000 : "nand.bootloader"
|
||||
0x00100000-0x00600000 : "nand.kernel"
|
||||
0x00600000-0x06600000 : "nand.rootfs"
|
||||
0x06600000-0x06e00000 : "nand.configure"
|
||||
0x06e00000-0x80000000 : "nand.userfs"
|
||||
|
||||
Creating 6 MTD partitions on "mxc_nor_flash.0":
|
||||
0x00000000-0x00080000 : "Bootloader"
|
||||
0x00080000-0x00480000 : "nor.Kernel"
|
||||
0x00480000-0x02280000 : "nor.userfs"
|
||||
0x02280000-0x03e80000 : "nor.rootfs"
|
||||
0x01fe0000-0x01fe3000 : "FIS directory"
|
||||
0x01fff000-0x04000000 : "Redboot config"
|
||||
|
||||
NAND partitions can be recognized enabling in kernel CONFIG_MTD_REDBOOT_PARTS.
|
||||
For this board, CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK should be set to 2.
|
||||
|
||||
However, the setup in redboot is not correct and does not use the whole flash.
|
||||
|
||||
Better solution is to use the kernel parameter mtdparts.
|
||||
Here the resulting script to be defined in RedBoot with fconfig:
|
||||
|
||||
load -r -b 0x100000 sbabic/mx35pdk/zImage.2.6.37
|
||||
exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/arm rw ip=dhcp mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"
|
||||
|
||||
Flashing U-Boot
|
||||
--------------------------------
|
||||
|
||||
There are two options: the original bootloader in NAND can be replaced with
|
||||
u-boot, or u-boot can be stored on the NOR flash without erasing
|
||||
the delivered bootloader.
|
||||
The boot storage can be select using the switches on the personality board
|
||||
(SW1-SW2) and on the DEBUG board (SW4-SW10).
|
||||
|
||||
The second option is to be preferred if you have not a JTAG debugger.
|
||||
If something goes wrong flashing the bootloader, it is always possible to
|
||||
recover the board booting from the other device.
|
||||
|
||||
Replacing the bootloader on the NAND
|
||||
--------------------------------------
|
||||
To replace RedBoot with U-Boot, the easy way is to do this in linux.
|
||||
Start the kernel with the suggested options. Make sure to have set the
|
||||
mtdparts exactly as described, because this matches the layout on the
|
||||
mx35pdk.
|
||||
|
||||
You should see in your boot log the following entries for the NAND
|
||||
flash:
|
||||
|
||||
5 cmdlinepart partitions found on MTD device mxc_nand
|
||||
Creating 5 MTD partitions on "mxc_nand":
|
||||
0x000000000000-0x000000100000 : "boot"
|
||||
0x000000100000-0x000000600000 : "linux"
|
||||
0x000000600000-0x000006600000 : "root"
|
||||
0x000006600000-0x000006e00000 : "cfg"
|
||||
0x000006e00000-0x000080000000 : "user"
|
||||
|
||||
You can use the utilities flash_eraseall and nandwrite to put
|
||||
u-boot on the NAND. The bootloader is marked as "boot", and 1MB is
|
||||
reserved. If everything is correct, this partition is accessed as
|
||||
/dev/mtd4. However, check if it is correct with "cat /proc/mtd" and
|
||||
get the device node from the partition name:
|
||||
|
||||
$ cat /proc/mtd | grep boot
|
||||
|
||||
I suggest you try the utilities on a different partition to be sure
|
||||
if everything works correctly. If not, and you remove RedBoot, you have to
|
||||
reinstall it using the ATK tool as suggested by Freescale, or using a
|
||||
JTAG debugger.
|
||||
|
||||
I report the versions of the utilities I used (they are provided with ELDK):
|
||||
|
||||
-bash-3.2# nandwrite --version
|
||||
nandwrite $Revision: 1.32 $
|
||||
|
||||
flash_eraseall --version
|
||||
flash_eraseall $Revision: 1.22 $
|
||||
|
||||
nandwrite reports a warning if the file to be saved is not sector aligned.
|
||||
This should have no consequences, but I preferred to pad u-boot.bin
|
||||
to get no problem at all.
|
||||
$ dd if=/dev/zero of=zeros bs=1 count=74800
|
||||
$ cat u-boot.bin zeros > u-boot-padded.bin
|
||||
|
||||
To erase the partition:
|
||||
$ flash_eraseall /dev/mtd4
|
||||
|
||||
Writing u-boot:
|
||||
|
||||
$ nandwrite /dev/mtd4 u-boot-padded.bin
|
||||
|
||||
Now U-Boot is stored on the booting partition.
|
||||
|
||||
To boot from NAND, you have to select the switches as follows:
|
||||
|
||||
Personality board
|
||||
SW2 1, 4, 5 on
|
||||
2, 3, 6, 7, 8 off
|
||||
SW1 all off
|
||||
|
||||
Debug Board:
|
||||
SW5 0
|
||||
SW6 0
|
||||
SW7 0
|
||||
SW8 1
|
||||
SW9 1
|
||||
SW10 0
|
||||
|
||||
|
||||
Saving U-Boot in the NOR flash
|
||||
---------------------------------
|
||||
|
||||
The procedure to save in the NOR flash is quite the same as to write into the NAND.
|
||||
|
||||
Check the partition for boot in the NOR flash. Setting the mtdparts as reported,
|
||||
the boot partition should be /dev/mtd0.
|
||||
|
||||
Creating 6 MTD partitions on "mxc_nor_flash.0":
|
||||
0x00000000-0x00080000 : "Bootloader"
|
||||
0x00080000-0x00480000 : "nor.Kernel"
|
||||
0x00480000-0x02280000 : "nor.userfs"
|
||||
0x02280000-0x03e80000 : "nor.rootfs"
|
||||
0x01fe0000-0x01fe3000 : "FIS directory"
|
||||
0x01fff000-0x04000000 : "Redboot config"
|
||||
|
||||
To erase the whole partition:
|
||||
$ flash_eraseall /dev/mtd0
|
||||
|
||||
Writing u-boot:
|
||||
dd if=u-boot.bin of=/dev/mtd0
|
||||
|
||||
To boot from NOR, you have to select the switches as follows:
|
||||
|
||||
Personality board
|
||||
SW2 all off
|
||||
SW1 all off
|
||||
|
||||
Debug Board:
|
||||
SW5 0
|
||||
SW6 0
|
||||
SW7 0
|
||||
SW8 1
|
||||
SW9 1
|
||||
SW10 0
|
||||
|
|
@ -0,0 +1,303 @@
|
|||
/*
|
||||
* (C) Copyright 2010, Stefano Babic <sbabic@denx.de>
|
||||
*
|
||||
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
*
|
||||
* Configuration for the MX35pdk Freescale board.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
|
||||
#define CONFIG_MX35
|
||||
#define CONFIG_MX35_HCLK_FREQ 24000000
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
/* Set TEXT at the beginning of the NOR flash */
|
||||
#define CONFIG_SYS_TEXT_BASE 0xA0000000
|
||||
|
||||
#define CONFIG_SYS_64BIT_VSPRINTF
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_REVISION_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MX35_PORT1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0xfe
|
||||
#define CONFIG_MXC_SPI
|
||||
|
||||
|
||||
/*
|
||||
* PMIC Configs
|
||||
*/
|
||||
#define CONFIG_FSL_PMIC
|
||||
#define CONFIG_FSL_PMIC_I2C
|
||||
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
|
||||
|
||||
/*
|
||||
* MFD MC9SDZ60
|
||||
*/
|
||||
#define CONFIG_FSL_MC9SDZ60
|
||||
#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69
|
||||
|
||||
/*
|
||||
* UART (console)
|
||||
*/
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_SYS_MX35_UART1
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/*
|
||||
* Command definition
|
||||
*/
|
||||
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_DNS
|
||||
|
||||
#define CONFIG_CMD_NAND
|
||||
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_NET_RETRY_COUNT 100
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
|
||||
|
||||
/*
|
||||
* Ethernet on the debug board (SMC911)
|
||||
*/
|
||||
#define CONFIG_SMC911X
|
||||
#define CONFIG_SMC911X_16_BIT 1
|
||||
#define CONFIG_SMC911X_BASE CS5_BASE_ADDR
|
||||
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_ETHPRIME
|
||||
|
||||
/*
|
||||
* Ethernet on SOC (FEC)
|
||||
*/
|
||||
#define CONFIG_FEC_MXC
|
||||
#define IMX_FEC_BASE FEC_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1F
|
||||
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_DISCOVER_PHY
|
||||
|
||||
#define CONFIG_ARP_TIMEOUT 200UL
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "MX35 U-Boot > "
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x10000
|
||||
|
||||
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
|
||||
/*
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
|
||||
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
|
||||
#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
|
||||
#define iomem_valid_addr(addr, size) \
|
||||
(addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_GBL_DATA_OFFSET)
|
||||
|
||||
/*
|
||||
* MTD Command for mtdparts
|
||||
*/
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_MTD_DEVICE
|
||||
#define CONFIG_FLASH_CFI_MTD
|
||||
#define CONFIG_MTD_PARTITIONS
|
||||
#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:1m(boot),5m(linux)," \
|
||||
"96m(root),8m(cfg),1938m(user);" \
|
||||
"physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
/* Monitor at beginning of flash */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
|
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
|
||||
CONFIG_SYS_MONITOR_LEN)
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
|
||||
#if defined(CONFIG_FSL_ENV_IN_NAND)
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_OFFSET (1024 * 1024)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* CFI FLASH driver setup
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
|
||||
/* A non-standard buffered write algorithm */
|
||||
#define CONFIG_FLASH_SPANSION_S29WS_N
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
|
||||
|
||||
/*
|
||||
* NAND FLASH driver setup
|
||||
*/
|
||||
#define CONFIG_NAND_MXC
|
||||
#define CONFIG_NAND_MXC_V1_1
|
||||
#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
|
||||
#define CONFIG_MXC_NAND_HWECC
|
||||
#define CONFIG_SYS_NAND_LARGEPAGE
|
||||
|
||||
/*
|
||||
* Default environment and default scripts
|
||||
* to update uboot and load kernel
|
||||
*/
|
||||
#define xstr(s) str(s)
|
||||
#define str(s) #s
|
||||
|
||||
#define CONFIG_HOSTNAME "mx35pdk"
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth1\0" \
|
||||
"ethprime=smc911x\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip_sta=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
|
||||
"addip=if test -n ${ipdyn};then run addip_dyn;" \
|
||||
"else run addip_sta;fi\0" \
|
||||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"addtty=setenv bootargs ${bootargs}" \
|
||||
" console=ttymxc0,${baudrate}\0" \
|
||||
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
|
||||
"loadaddr=80800000\0" \
|
||||
"kernel_addr_r=80800000\0" \
|
||||
"hostname=" xstr(CONFIG_HOSTNAME) "\0" \
|
||||
"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
|
||||
"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
|
||||
"flash_self=run ramargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
|
||||
"run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr_r}\0" \
|
||||
"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
|
||||
"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
|
||||
"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr} ${u-boot}\0" \
|
||||
"uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
|
||||
"update=protect off ${uboot_addr} +40000;" \
|
||||
"erase ${uboot_addr} +40000;" \
|
||||
"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
|
||||
"upd=if run load;then echo Updating u-boot;if run update;" \
|
||||
"then echo U-Boot updated;" \
|
||||
"else echo Error updating u-boot !;" \
|
||||
"echo Board without bootloader !!;" \
|
||||
"fi;" \
|
||||
"else echo U-Boot not downloaded..exiting;fi\0" \
|
||||
"bootcmd=run net_nfs\0"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue