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ppc4xx: Fix problem with DIMMs with 8 banks in 44x_spd_ddr2.c 

This patch fixes a problem with DIMMs that have 8 banks. Now the
MCIF0_MBxCF register will be setup correctly for this setup too.

This was noticed with the 512MB DIMM on Canyonlands/Glacier.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2008-04-30 10:49:43 +02:00
parent 7661729935
commit ea9202a659
1 changed files with 5 additions and 2 deletions
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7
cpu/ppc4xx/44x_spd_ddr2.c
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@ -1,7 +1,10 @@
/* /*
* cpu/ppc4xx/44x_spd_ddr2.c * cpu/ppc4xx/44x_spd_ddr2.c
* This SPD SDRAM detection code supports AMCC PPC44x cpu's with a * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
* DDR2 controller (non Denali Core). Those are 440SP/SPe. * DDR2 controller (non Denali Core). Those currently are:
*
* 405: 405EX
* 440/460: 440SP/440SPe/460EX/460GT
* *
* (C) Copyright 2007-2008 * (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de. * Stefan Roese, DENX Software Engineering, sr@denx.de.
@ -2078,7 +2081,7 @@ static void program_bxcf(unsigned long *dimm_populated,
if (num_banks == 4) if (num_banks == 4)
ind = 0; ind = 0;
else else
ind = 5; ind = 5 << 8;
switch (num_col_addr) { switch (num_col_addr) {
case 0x08: case 0x08:
mode |= (SDRAM_BXCF_M_AM_0 + ind); mode |= (SDRAM_BXCF_M_AM_0 + ind);