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keystone2: use readl/writel functions instead of redefinition 

There is no reason to redefine pure readl/writel functions.
So remove this redundancy.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Vitaly Andrianov <vitalya@ti.com>
This commit is contained in:
Khoronzhuk, Ivan 2014-08-28 16:07:45 +03:00 committed by Tom Rini
parent 09642269a6
commit e6c9428a2f
3 changed files with 36 additions and 50 deletions
arch/arm
cpu/armv7/keystone
psc.c
include/asm/arch-keystone
emac_defs.h
drivers/net
keystone_net.c

44
arch/arm/cpu/armv7/keystone/psc.c
View File

@ -13,9 +13,6 @@
#include <asm/processor.h>
#include <asm/arch/psc_defs.h>
#define DEVICE_REG32_R(addr) __raw_readl((u32 *)(addr))
#define DEVICE_REG32_W(addr, val) __raw_writel(val, (u32 *)(addr))
int psc_delay(void)
{
udelay(10);
@ -51,7 +48,7 @@ int psc_wait(u32 domain_num)
retry = 0;
do {
ptstat = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PSTAT);
ptstat = __raw_readl(KS2_PSC_BASE + PSC_REG_PSTAT);
ptstat = ptstat & (1 << domain_num);
} while ((ptstat != 0) && ((retry += psc_delay()) <
PSC_PTSTAT_TIMEOUT_LIMIT));
@ -67,8 +64,7 @@ u32 psc_get_domain_num(u32 mod_num)
u32 domain_num;
/* Get the power domain associated with the module number */
domain_num = DEVICE_REG32_R(KS2_PSC_BASE +
PSC_REG_MDCFG(mod_num));
domain_num = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
return domain_num;
@ -102,7 +98,7 @@ int psc_set_state(u32 mod_num, u32 state)
* Get the power domain associated with the module number, and reset
* isolation functionality
*/
v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(v);
reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v);
@ -119,24 +115,22 @@ int psc_set_state(u32 mod_num, u32 state)
* change is made if the new state is power down.
*/
if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
pdctl = DEVICE_REG32_R(KS2_PSC_BASE +
PSC_REG_PDCTL(domain_num));
pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
PSC_REG_VAL_PDCTL_NEXT_ON);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num),
pdctl);
__raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
}
/* Set the next state for the module to enabled/disabled */
mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
/* Trigger the enable */
ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1<<domain_num);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
__raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD);
/* Wait on the complete */
return psc_wait(domain_num);
@ -157,7 +151,7 @@ int psc_enable_module(u32 mod_num)
u32 mdctl;
/* Set the bit to apply reset */
mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
return 0;
@ -176,11 +170,11 @@ int psc_disable_module(u32 mod_num)
u32 mdctl;
/* Set the bit to apply reset */
mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl & 0x3f) == 0)
return 0;
mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
}
@ -199,11 +193,11 @@ int psc_set_reset_iso(u32 mod_num)
u32 mdctl;
/* Set the reset isolation bit */
mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
return 0;
@ -220,14 +214,14 @@ int psc_disable_domain(u32 domain_num)
u32 pdctl;
u32 ptcmd;
pdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
__raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1 << domain_num);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
__raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD);
return psc_wait(domain_num);
}

7
arch/arm/include/asm/arch-keystone/emac_defs.h
View File

@ -13,9 +13,6 @@
#include <asm/arch/hardware.h>
#include <asm/io.h>
#define DEVICE_REG32_R(a) readl(a)
#define DEVICE_REG32_W(a, v) writel(v, a)
#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900)
#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300)
#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00090100)
@ -182,8 +179,8 @@ struct mac_sl_cfg {
#endif
#define hw_config_streaming_switch() \
DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, \
DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI);
writel(DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI,\
DEVICE_PSTREAM_CFG_REG_ADDR);
/* EMAC MDIO Registers Structure */
struct mdio_regs {

35
drivers/net/keystone_net.c
View File

@ -290,13 +290,12 @@ int mac_sl_reset(u32 port)
return GMACSL_RET_INVALID_PORT;
/* Set the soft reset bit */
DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) +
CPGMACSL_REG_RESET, CPGMAC_REG_RESET_VAL_RESET);
writel(CPGMAC_REG_RESET_VAL_RESET,
DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
/* Wait for the bit to clear */
for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
v = DEVICE_REG32_R(DEVICE_EMACSL_BASE(port) +
CPGMACSL_REG_RESET);
v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
CPGMAC_REG_RESET_VAL_RESET)
return GMACSL_RET_OK;
@ -321,8 +320,7 @@ int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
/* Must wait if the device is undergoing reset */
for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
v = DEVICE_REG32_R(DEVICE_EMACSL_BASE(port) +
CPGMACSL_REG_RESET);
v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
CPGMAC_REG_RESET_VAL_RESET)
break;
@ -331,11 +329,8 @@ int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN,
cfg->max_rx_len);
DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL,
cfg->ctl);
writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
return ret;
}
@ -345,24 +340,24 @@ int ethss_config(u32 ctl, u32 max_pkt_size)
u32 i;
/* Max length register */
DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_MAXLEN, max_pkt_size);
writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
/* Control register */
DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_CTL, ctl);
writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
/* All statistics enabled by default */
DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN,
CPSW_REG_VAL_STAT_ENABLE_ALL);
writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
/* Reset and enable the ALE */
DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL,
CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
CPSW_REG_VAL_ALE_CTL_BYPASS);
writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
CPSW_REG_VAL_ALE_CTL_BYPASS,
DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
/* All ports put into forward mode */
for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i),
CPSW_REG_VAL_PORTCTL_FORWARD_MODE);
writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
return 0;
}