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Patch by Andrea Marson, 11 Jun 2004: 

Update for PPChameleon board:
- support for SysClk @ 25MHz
- support for Silicon Motion SM712 VGA controller
- some clean ups
This commit is contained in:
wdenk 2004-07-01 21:40:08 +00:00
parent 93f6a6771b
commit e55ca7e262
9 changed files with 215 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
CHANGELOG
View File

@ -2,6 +2,12 @@
Changes since U-Boot 1.1.1: Changes since U-Boot 1.1.1:
====================================================================== ======================================================================
* Patch by Andrea Marson, 11 Jun 2004:
Update for PPChameleon board:
- support for SysClk @ 25MHz
- support for Silicon Motion SM712 VGA controller
- some clean ups
* Patches by Richard Woodruff, 10 Jun 2004: * Patches by Richard Woodruff, 10 Jun 2004:
- fix problems with examples/stubs.c for GCC >= 3.4 - fix problems with examples/stubs.c for GCC >= 3.4
- fix problems with gd initialization - fix problems with gd initialization

10
CREDITS
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@ -254,6 +254,11 @@ N: Dan Malek
E: dan@netx4.com E: dan@netx4.com
D: FADSROM, the grandfather of all of this D: FADSROM, the grandfather of all of this
N: Andrea "llandre" Marson
E: andrea.marson@dave-tech.it
D: Port to PPChameleonEVB board
W: www.dave-tech.it
N: Reinhard Meyer N: Reinhard Meyer
E: r.meyer@emk-elektronik.de E: r.meyer@emk-elektronik.de
D: Port to EMK TOP860 Module D: Port to EMK TOP860 Module
@ -338,6 +343,11 @@ N: Kurt Stremerch
E: kurt@exys.be E: kurt@exys.be
D: Support for Exys XSEngine board D: Support for Exys XSEngine board
N: Andrea Scian
E: andrea.scian@dave-tech.it
D: Port to B2 board
W: www.dave-tech.it
N: Rob Taylor N: Rob Taylor
E: robt@flyingpig.com E: robt@flyingpig.com
D: Port to MBX860T and Sandpoint8240 D: Port to MBX860T and Sandpoint8240

8
MAINTAINERS
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@ -185,6 +185,10 @@ Eran Man <eran@nbase.co.il>
EVB64260_750CX MPC750CX EVB64260_750CX MPC750CX
Andrea "llandre" Marson <andrea.marson@dave-tech.it>
PPChameleonEVB PPC405EP
Reinhard Meyer <r.meyer@emk-elektronik.de> Reinhard Meyer <r.meyer@emk-elektronik.de>
TOP860 MPC860T TOP860 MPC860T
@ -373,6 +377,10 @@ Robert Schwebel <r.schwebel@pengutronix.de>
csb226 xscale csb226 xscale
innokom xscale innokom xscale
Andrea Scian <andrea.scian@dave-tech.it>
B2 ARM7TDMI (S3C44B0X)
Alex Züpke <azu@sysgo.de> Alex Züpke <azu@sysgo.de>
lart SA1100 lart SA1100

20
Makefile
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@ -606,7 +606,7 @@ wtk_config: unconfig
######################################################################### #########################################################################
## PPC4xx Systems ## PPC4xx Systems
######################################################################### #########################################################################
xtract_4xx = $(subst _MODEL_BA,,$(subst _MODEL_ME,,$(subst _MODEL_HI,,$(subst _config,,$1)))) xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(subst _config,,$1))))))
ADCIOP_config: unconfig ADCIOP_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx adciop esd @./mkconfig $(@:_config=) ppc ppc4xx adciop esd
@ -706,10 +706,12 @@ PLU405_config: unconfig
PMC405_config: unconfig PMC405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx pmc405 esd @./mkconfig $(@:_config=) ppc ppc4xx pmc405 esd
PPChameleonEVB_MODEL_BA_config \ PPChameleonEVB_BA_25_config \
PPChameleonEVB_MODEL_ME_config \ PPChameleonEVB_ME_25_config \
PPChameleonEVB_MODEL_HI_config \ PPChameleonEVB_HI_25_config \
PPChameleonEVB_config: unconfig PPChameleonEVB_BA_33_config \
PPChameleonEVB_ME_33_config \
PPChameleonEVB_HI_33_config: unconfig
@ >include/config.h @ >include/config.h
@[ -z "$(findstring _MODEL_BA,$@)" ] || \ @[ -z "$(findstring _MODEL_BA,$@)" ] || \
{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>include/config.h ; \ { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>include/config.h ; \
@ -723,6 +725,14 @@ PPChameleonEVB_config: unconfig
{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>include/config.h ; \ { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>include/config.h ; \
echo "... HIGH-END model" ; \ echo "... HIGH-END model" ; \
} }
@[ -z "$(findstring _25,$@)" ] || \
{ echo "#define CONFIG_PPCHAMELEON_CLK_25" >>include/config.h ; \
echo " SysClk = 25MHz" ; \
}
@[ -z "$(findstring _33,$@)" ] || \
{ echo "#define CONFIG_PPCHAMELEON_CLK_33" >>include/config.h ; \
echo " SysClk = 33MHz" ; \
}
@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave @./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
VOH405_config: unconfig VOH405_config: unconfig

72
board/dave/PPChameleonEVB/PPChameleonEVB.c
View File

@ -29,22 +29,9 @@
#include <command.h> #include <command.h>
#include <malloc.h> #include <malloc.h>
/* ------------------------------------------------------------------------- */ /* ------------------------------------------------------------------------- */
#if 0
#define FPGA_DEBUG
#endif
/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
{
#include "fpgadata.c"
};
/*
* include common fpga code (for esd boards)
*/
#include "../common/fpga.c"
/* Prototypes */ /* Prototypes */
@ -60,13 +47,13 @@ int board_early_init_f (void)
* IRQ 0-15 405GP internally generated; active high; level sensitive * IRQ 0-15 405GP internally generated; active high; level sensitive
* IRQ 16 405GP internally generated; active low; level sensitive * IRQ 16 405GP internally generated; active low; level sensitive
* IRQ 17-24 RESERVED * IRQ 17-24 RESERVED
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive * IRQ 25 (EXT IRQ 0)
* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive * IRQ 26 (EXT IRQ 1)
* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive * IRQ 27 (EXT IRQ 2)
* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive * IRQ 28 (EXT IRQ 3)
* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive * IRQ 29 (EXT IRQ 4)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 30 (EXT IRQ 5)
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive * IRQ 31 (EXT IRQ 6)
*/ */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */ mtdcr(uicer, 0x00000000); /* disable all ints */
@ -268,8 +255,13 @@ nand_init(void)
{ {
ulong totlen = 0; ulong totlen = 0;
#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) || \ /*
The HI model is equipped with a large block NAND chip not supported yet
by U-Boot
(CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
*/
#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE); debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
totlen += nand_probe (CFG_NAND0_BASE); totlen += nand_probe (CFG_NAND0_BASE);
#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */ #endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */
@ -280,3 +272,39 @@ nand_init(void)
printf ("%4lu MB\n", totlen >>20); printf ("%4lu MB\n", totlen >>20);
} }
#endif #endif
#ifdef CONFIG_CFB_CONSOLE
# ifdef CONFIG_CONSOLE_EXTRA_INFO
# include <video_fb.h>
extern GraphicDevice smi;
void video_get_info_str (int line_number, char *info)
{
uint pvr = get_pvr ();
/* init video info strings for graphic console */
switch (line_number) {
case 1:
switch (pvr) {
case PVR_405EP_RB:
sprintf (info, " IBM PowerPC 405EP Rev. B");
break;
default:
sprintf (info, " IBM PowerPC 405EP Rev. <unknown>");
break;
}
return;
case 2:
sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it");
return;
case 3:
sprintf (info, " %s", smi.modeIdent);
return;
}
/* no more info lines */
*info = 0;
return;
}
# endif /* CONFIG_CONSOLE_EXTRA_INFO */
#endif /* CONFIG_CFB_CONSOLE */

9
board/dave/PPChameleonEVB/flash.c
View File

@ -50,6 +50,9 @@ unsigned long flash_init (void)
unsigned long base; unsigned long base;
int size_val = 0; int size_val = 0;
debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
debug("[%s, %d] flash_info = 0x%08X ...\n", __FUNCTION__, __LINE__, flash_info);
/* Init: no FLASHes known */ /* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].flash_id = FLASH_UNKNOWN;
@ -57,6 +60,7 @@ unsigned long flash_init (void)
/* Static FLASH Bank configuration here - FIXME XXX */ /* Static FLASH Bank configuration here - FIXME XXX */
debug("[%s, %d] Calling flash_get_size ...\n", __FUNCTION__, __LINE__);
size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) { if (flash_info[0].flash_id == FLASH_UNKNOWN) {
@ -64,8 +68,11 @@ unsigned long flash_init (void)
size, size<<20); size, size<<20);
} }
debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
/* Setup offsets */ /* Setup offsets */
flash_get_offsets (-size, &flash_info[0]); flash_get_offsets (-size, &flash_info[0]);
debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
/* Re-do sizing to get full correct info */ /* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr); mtdcr(ebccfga, pb0cr);
@ -91,6 +98,7 @@ unsigned long flash_init (void)
} }
pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17); pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17);
mtdcr(ebccfgd, pbcr); mtdcr(ebccfgd, pbcr);
debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
/* Monitor protection ON by default */ /* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET, (void)flash_protect(FLAG_PROTECT_SET,
@ -98,6 +106,7 @@ unsigned long flash_init (void)
0xffffffff, 0xffffffff,
&flash_info[0]); &flash_info[0]);
debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
flash_info[0].size = size; flash_info[0].size = size;
return (size); return (size);

2
board/dave/common/flash.c
View File

@ -220,6 +220,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
ulong base = (ulong)addr; ulong base = (ulong)addr;
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr; volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
/* Write auto select command: read Manufacturer ID */ /* Write auto select command: read Manufacturer ID */
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;

9
cpu/ppc4xx/speed.c
View File

@ -383,8 +383,13 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo)
*/ */
pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1; pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1;
if (pllmr1 & PLLMR1_SSCS_MASK) { if (pllmr1 & PLLMR1_SSCS_MASK) {
sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) /*
/ pllmr0_ccdv; * This is true if FWDVA == FWDVB:
* sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv)
* / pllmr0_ccdv;
*/
sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv * sysInfo->pllFwdDivB)
/ sysInfo->pllFwdDiv / pllmr0_ccdv;
} else { } else {
sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv; sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv;
} }

149
include/configs/PPChameleonEVB.h
View File

@ -38,6 +38,18 @@
#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
#endif #endif
/* Only one of the following two symbols must be defined (default is 25 MHz)
* CONFIG_PPCHAMELEON_CLK_25
* CONFIG_PPCHAMELEON_CLK_33
*/
#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
#error "* Two external frequencies (SysClk) are defined! *"
#endif
#undef CONFIG_PPCHAMELEON_SMI712
/* /*
* Debug stuff * Debug stuff
*/ */
@ -60,7 +72,14 @@
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#ifdef CONFIG_PPCHAMELEON_CLK_25
#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
#else
#error "* External frequency (SysClk) not defined! *"
#endif
#define CONFIG_BAUDRATE 115200 #define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
@ -75,7 +94,6 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#undef CONFIG_EXT_PHY #undef CONFIG_EXT_PHY
#define CONFIG_NET_MULTI 1 #define CONFIG_NET_MULTI 1
@ -184,7 +202,6 @@
#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ #define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ #define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
#define NAND_DISABLE_CE(nand) do \ #define NAND_DISABLE_CE(nand) do \
{ \ { \
switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
@ -211,7 +228,6 @@
} \ } \
} while(0) } while(0)
#define NAND_CTL_CLRALE(nandptr) do \ #define NAND_CTL_CLRALE(nandptr) do \
{ \ { \
switch((unsigned long)nandptr) \ switch((unsigned long)nandptr) \
@ -292,9 +308,10 @@
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
@ -349,12 +366,23 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Environment Variable setup * Environment Variable setup
*/ */
#ifdef ENVIRONMENT_IN_EEPROM
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
#else /* DEFAULT: environment in flash, using redundand flash sectors */
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */ #define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
#define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/ #define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
#define CFG_ENV_ADDR_REDUND 0xFFFFA000 #define CFG_ENV_ADDR_REDUND 0xFFFFA000
#define CFG_ENV_SIZE_REDUND 0x2000 #define CFG_ENV_SIZE_REDUND 0x2000
#endif /* ENVIRONMENT_IN_EEPROM */
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CFG_NVRAM_SIZE 242 /* NVRAM size */ #define CFG_NVRAM_SIZE 242 /* NVRAM size */
@ -414,23 +442,21 @@
#define CFG_EBC_PB3AP 0x92015480 #define CFG_EBC_PB3AP 0x92015480
#define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */ #define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
#ifdef CONFIG_PPCHAMELEON_SMI712
#if 0 /* Roese */ /*
/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ * Video console (graphic: SMI LynxEM)
#define CFG_EBC_PB1AP 0x92015480 */
#define CFG_EBC_PB1CR 0xFF858000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ #define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
/* Memory Bank 2 (CAN0, 1) initialization */ #define CONFIG_VIDEO_SMI_LYNXEM
#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ #define CONFIG_VIDEO_LOGO
#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ /*#define CONFIG_VIDEO_BMP_LOGO*/
#define CONFIG_CONSOLE_EXTRA_INFO
/* Memory Bank 3 (CompactFlash IDE) initialization */ #define CONFIG_VGA_AS_SINGLE_DEVICE
#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ #define CFG_ISA_IO 0xE8000000
/* see also drivers/videomodes.c */
/* Memory Bank 4 (NVRAM/RTC) initialization */ #define CFG_DEFAULT_VIDEO_MODE 0x303
#define CFG_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
#endif #endif
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
@ -485,6 +511,7 @@
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@ -525,7 +552,6 @@
/*--------------------------------------------------------------------*/ /*--------------------------------------------------------------------*/
#ifdef CONFIG_NO_SERIAL_EEPROM #ifdef CONFIG_NO_SERIAL_EEPROM
/* /*
!----------------------------------------------------------------------- !-----------------------------------------------------------------------
! Defines for entry options. ! Defines for entry options.
@ -537,7 +563,6 @@
#define DIMM_READ_ADDR 0xAB #define DIMM_READ_ADDR 0xAB
#define DIMM_WRITE_ADDR 0xAA #define DIMM_WRITE_ADDR 0xAA
#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
@ -649,50 +674,92 @@
#define PLL_PCIDIV_3 0x00000002 #define PLL_PCIDIV_3 0x00000002
#define PLL_PCIDIV_4 0x00000003 #define PLL_PCIDIV_4 0x00000003
#ifdef CONFIG_PPCHAMELEON_CLK_25
/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
PLL_MALDIV_1 | PLL_PCIDIV_2)
#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
#define PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
PLL_MALDIV_1 | PLL_PCIDIV_4) PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
PLL_MALDIV_1 | PLL_PCIDIV_4) PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
PLL_MALDIV_1 | PLL_PCIDIV_4) PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
PLL_MALDIV_1 | PLL_PCIDIV_2) PLL_MALDIV_1 | PLL_PCIDIV_2)
#define PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
#else
#error "* External frequency (SysClk) not defined! *"
#endif
#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) #if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
/* Model HI */ /* Model HI */
#define PLLMR0_DEFAULT PLLMR0_333_111_37_55_55 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
#define PLLMR1_DEFAULT PLLMR1_333_111_37_55_55 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
#define CFG_OPB_FREQ 55555555
/* Model ME */ /* Model ME */
#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
#define PLLMR0_DEFAULT PLLMR0_266_133_33_66_33 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
#define PLLMR1_DEFAULT PLLMR1_266_133_33_66_33 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
#define CFG_OPB_FREQ 66666666
#else #else
/* Model BA (default) */ /* Model BA (default) */
#define PLLMR0_DEFAULT PLLMR0_133_133_33_66_33 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
#define PLLMR1_DEFAULT PLLMR1_133_133_33_66_33 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
#define CFG_OPB_FREQ 66666666
#endif
#endif #endif
#endif /* CONFIG_NO_SERIAL_EEPROM */ #define CONFIG_JFFS2_NAND 0 /* jffs2 on nand support */
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */ #define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */
#define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */ #define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */
#define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */ #define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */