avr32: delete non generic board's atstk100{3, 4, 6}
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This commit is contained in:
Andreas Bießmann
parent
c62d2f8fc5
commit
e5354b8a9e
|
|
@ -17,15 +17,6 @@ config TARGET_ATNGW100MKII
|
||||||
config TARGET_ATSTK1002
|
config TARGET_ATSTK1002
|
||||||
bool "Support atstk1002"
|
bool "Support atstk1002"
|
||||||
|
|
||||||
config TARGET_ATSTK1003
|
|
||||||
bool "Support atstk1003"
|
|
||||||
|
|
||||||
config TARGET_ATSTK1004
|
|
||||||
bool "Support atstk1004"
|
|
||||||
|
|
||||||
config TARGET_ATSTK1006
|
|
||||||
bool "Support atstk1006"
|
|
||||||
|
|
||||||
config TARGET_GRASSHOPPER
|
config TARGET_GRASSHOPPER
|
||||||
bool "Support grasshopper"
|
bool "Support grasshopper"
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -13,51 +13,3 @@ config SYS_CONFIG_NAME
|
||||||
default "atstk1002"
|
default "atstk1002"
|
||||||
|
|
||||||
endif
|
endif
|
||||||
|
|
||||||
if TARGET_ATSTK1003
|
|
||||||
|
|
||||||
config SYS_BOARD
|
|
||||||
default "atstk1000"
|
|
||||||
|
|
||||||
config SYS_VENDOR
|
|
||||||
default "atmel"
|
|
||||||
|
|
||||||
config SYS_SOC
|
|
||||||
default "at32ap700x"
|
|
||||||
|
|
||||||
config SYS_CONFIG_NAME
|
|
||||||
default "atstk1003"
|
|
||||||
|
|
||||||
endif
|
|
||||||
|
|
||||||
if TARGET_ATSTK1004
|
|
||||||
|
|
||||||
config SYS_BOARD
|
|
||||||
default "atstk1000"
|
|
||||||
|
|
||||||
config SYS_VENDOR
|
|
||||||
default "atmel"
|
|
||||||
|
|
||||||
config SYS_SOC
|
|
||||||
default "at32ap700x"
|
|
||||||
|
|
||||||
config SYS_CONFIG_NAME
|
|
||||||
default "atstk1004"
|
|
||||||
|
|
||||||
endif
|
|
||||||
|
|
||||||
if TARGET_ATSTK1006
|
|
||||||
|
|
||||||
config SYS_BOARD
|
|
||||||
default "atstk1000"
|
|
||||||
|
|
||||||
config SYS_VENDOR
|
|
||||||
default "atmel"
|
|
||||||
|
|
||||||
config SYS_SOC
|
|
||||||
default "at32ap700x"
|
|
||||||
|
|
||||||
config SYS_CONFIG_NAME
|
|
||||||
default "atstk1006"
|
|
||||||
|
|
||||||
endif
|
|
||||||
|
|
|
||||||
|
|
@ -4,9 +4,3 @@ S: Orphan (since 2014-06)
|
||||||
F: board/atmel/atstk1000/
|
F: board/atmel/atstk1000/
|
||||||
F: include/configs/atstk1002.h
|
F: include/configs/atstk1002.h
|
||||||
F: configs/atstk1002_defconfig
|
F: configs/atstk1002_defconfig
|
||||||
F: include/configs/atstk1003.h
|
|
||||||
F: configs/atstk1003_defconfig
|
|
||||||
F: include/configs/atstk1004.h
|
|
||||||
F: configs/atstk1004_defconfig
|
|
||||||
F: include/configs/atstk1006.h
|
|
||||||
F: configs/atstk1006_defconfig
|
|
||||||
|
|
|
||||||
|
|
@ -30,32 +30,12 @@ struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct sdram_config sdram_config = {
|
static const struct sdram_config sdram_config = {
|
||||||
#if defined(CONFIG_ATSTK1006)
|
|
||||||
/* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
|
|
||||||
.data_bits = SDRAM_DATA_32BIT,
|
.data_bits = SDRAM_DATA_32BIT,
|
||||||
.row_bits = 13,
|
|
||||||
.col_bits = 9,
|
|
||||||
.bank_bits = 2,
|
|
||||||
.cas = 2,
|
|
||||||
.twr = 2,
|
|
||||||
.trc = 7,
|
|
||||||
.trp = 2,
|
|
||||||
.trcd = 2,
|
|
||||||
.tras = 4,
|
|
||||||
.txsr = 7,
|
|
||||||
/* 7.81 us */
|
|
||||||
.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
|
|
||||||
#else
|
|
||||||
/* MT48LC2M32B2P-5 (8 MB) on motherboard */
|
|
||||||
#ifdef CONFIG_ATSTK1004
|
|
||||||
.data_bits = SDRAM_DATA_16BIT,
|
|
||||||
#else
|
|
||||||
.data_bits = SDRAM_DATA_32BIT,
|
|
||||||
#endif
|
|
||||||
#ifdef CONFIG_ATSTK1000_16MB_SDRAM
|
#ifdef CONFIG_ATSTK1000_16MB_SDRAM
|
||||||
/* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
|
/* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
|
||||||
.row_bits = 12,
|
.row_bits = 12,
|
||||||
#else
|
#else
|
||||||
|
/* MT48LC2M32B2P-5 (8 MB) on motherboard */
|
||||||
.row_bits = 11,
|
.row_bits = 11,
|
||||||
#endif
|
#endif
|
||||||
.col_bits = 8,
|
.col_bits = 8,
|
||||||
|
|
@ -69,7 +49,6 @@ static const struct sdram_config sdram_config = {
|
||||||
.txsr = 5,
|
.txsr = 5,
|
||||||
/* 15.6 us */
|
/* 15.6 us */
|
||||||
.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
|
.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
|
||||||
#endif
|
|
||||||
};
|
};
|
||||||
|
|
||||||
int board_early_init_f(void)
|
int board_early_init_f(void)
|
||||||
|
|
|
||||||
|
|
@ -1,6 +0,0 @@
|
||||||
CONFIG_AVR32=y
|
|
||||||
CONFIG_TARGET_ATSTK1003=y
|
|
||||||
CONFIG_AUTOBOOT_KEYED=y
|
|
||||||
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
|
|
||||||
CONFIG_AUTOBOOT_DELAY_STR="d"
|
|
||||||
CONFIG_AUTOBOOT_STOP_STR=" "
|
|
||||||
|
|
@ -1,6 +0,0 @@
|
||||||
CONFIG_AVR32=y
|
|
||||||
CONFIG_TARGET_ATSTK1004=y
|
|
||||||
CONFIG_AUTOBOOT_KEYED=y
|
|
||||||
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
|
|
||||||
CONFIG_AUTOBOOT_DELAY_STR="d"
|
|
||||||
CONFIG_AUTOBOOT_STOP_STR=" "
|
|
||||||
|
|
@ -1,7 +0,0 @@
|
||||||
CONFIG_AVR32=y
|
|
||||||
CONFIG_CMD_NET=y
|
|
||||||
CONFIG_TARGET_ATSTK1006=y
|
|
||||||
CONFIG_AUTOBOOT_KEYED=y
|
|
||||||
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
|
|
||||||
CONFIG_AUTOBOOT_DELAY_STR="d"
|
|
||||||
CONFIG_AUTOBOOT_STOP_STR=" "
|
|
||||||
|
|
@ -1,150 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (C) 2007 Atmel Corporation
|
|
||||||
*
|
|
||||||
* Configuration settings for the ATSTK1003 CPU daughterboard
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
#ifndef __CONFIG_H
|
|
||||||
#define __CONFIG_H
|
|
||||||
|
|
||||||
#include <asm/arch/hardware.h>
|
|
||||||
|
|
||||||
#define CONFIG_AT32AP
|
|
||||||
#define CONFIG_AT32AP7001
|
|
||||||
#define CONFIG_ATSTK1003
|
|
||||||
#define CONFIG_ATSTK1000
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
|
|
||||||
* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
|
|
||||||
* PLL frequency.
|
|
||||||
* (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
|
|
||||||
*/
|
|
||||||
#define CONFIG_PLL
|
|
||||||
#define CONFIG_SYS_POWER_MANAGER
|
|
||||||
#define CONFIG_SYS_OSC0_HZ 20000000
|
|
||||||
#define CONFIG_SYS_PLL0_DIV 1
|
|
||||||
#define CONFIG_SYS_PLL0_MUL 7
|
|
||||||
#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
|
|
||||||
/*
|
|
||||||
* Set the CPU running at:
|
|
||||||
* PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CLKDIV_CPU 0
|
|
||||||
/*
|
|
||||||
* Set the HSB running at:
|
|
||||||
* PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CLKDIV_HSB 1
|
|
||||||
/*
|
|
||||||
* Set the PBA running at:
|
|
||||||
* PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CLKDIV_PBA 2
|
|
||||||
/*
|
|
||||||
* Set the PBB running at:
|
|
||||||
* PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CLKDIV_PBB 1
|
|
||||||
|
|
||||||
/* Reserve VM regions for SDRAM and NOR flash */
|
|
||||||
#define CONFIG_SYS_NR_VM_REGIONS 2
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The PLLOPT register controls the PLL like this:
|
|
||||||
* icp = PLLOPT<2>
|
|
||||||
* ivco = PLLOPT<1:0>
|
|
||||||
*
|
|
||||||
* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_PLL0_OPT 0x04
|
|
||||||
|
|
||||||
#define CONFIG_USART_BASE ATMEL_BASE_USART1
|
|
||||||
#define CONFIG_USART_ID 1
|
|
||||||
|
|
||||||
/* User serviceable stuff */
|
|
||||||
#define CONFIG_DOS_PARTITION
|
|
||||||
|
|
||||||
#define CONFIG_CMDLINE_TAG
|
|
||||||
#define CONFIG_SETUP_MEMORY_TAGS
|
|
||||||
#define CONFIG_INITRD_TAG
|
|
||||||
|
|
||||||
#define CONFIG_STACKSIZE (2048)
|
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 115200
|
|
||||||
#define CONFIG_BOOTARGS \
|
|
||||||
"console=ttyS0 root=/dev/mmcblk0p1 rootwait"
|
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND \
|
|
||||||
"mmc rescan; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm"
|
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 1
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration.
|
|
||||||
*/
|
|
||||||
#include <config_cmd_default.h>
|
|
||||||
|
|
||||||
#define CONFIG_CMD_ASKENV
|
|
||||||
#define CONFIG_CMD_EXT2
|
|
||||||
#define CONFIG_CMD_FAT
|
|
||||||
#define CONFIG_CMD_JFFS2
|
|
||||||
#define CONFIG_CMD_MMC
|
|
||||||
|
|
||||||
#undef CONFIG_CMD_FPGA
|
|
||||||
#undef CONFIG_CMD_NFS
|
|
||||||
#undef CONFIG_CMD_SETGETDCR
|
|
||||||
#undef CONFIG_CMD_XIMG
|
|
||||||
|
|
||||||
#define CONFIG_ATMEL_USART
|
|
||||||
#define CONFIG_PORTMUX_PIO
|
|
||||||
#define CONFIG_SYS_HSDRAMC
|
|
||||||
#define CONFIG_MMC
|
|
||||||
#define CONFIG_GENERIC_ATMEL_MCI
|
|
||||||
#define CONFIG_GENERIC_MMC
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DCACHE_LINESZ 32
|
|
||||||
#define CONFIG_SYS_ICACHE_LINESZ 32
|
|
||||||
|
|
||||||
#define CONFIG_NR_DRAM_BANKS 1
|
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_CFI
|
|
||||||
#define CONFIG_FLASH_CFI_DRIVER
|
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_BASE 0x00000000
|
|
||||||
#define CONFIG_SYS_FLASH_SIZE 0x800000
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 135
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x00000000
|
|
||||||
|
|
||||||
#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
|
|
||||||
#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
|
|
||||||
|
|
||||||
#define CONFIG_ENV_IS_IN_FLASH
|
|
||||||
#define CONFIG_ENV_SIZE 65536
|
|
||||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MALLOC_LEN (256*1024)
|
|
||||||
|
|
||||||
/* Allow 4MB for the kernel run-time image */
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
|
|
||||||
#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
|
|
||||||
|
|
||||||
/* Other configuration settings that shouldn't have to change all that often */
|
|
||||||
#define CONFIG_SYS_PROMPT "U-Boot> "
|
|
||||||
#define CONFIG_SYS_CBSIZE 256
|
|
||||||
#define CONFIG_SYS_MAXARGS 16
|
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
|
||||||
#define CONFIG_SYS_LONGHELP
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
|
|
||||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
|
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
|
||||||
|
|
@ -1,150 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (C) 2007 Atmel Corporation
|
|
||||||
*
|
|
||||||
* Configuration settings for the ATSTK1003 CPU daughterboard
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
#ifndef __CONFIG_H
|
|
||||||
#define __CONFIG_H
|
|
||||||
|
|
||||||
#include <asm/arch/hardware.h>
|
|
||||||
|
|
||||||
#define CONFIG_AT32AP
|
|
||||||
#define CONFIG_AT32AP7002
|
|
||||||
#define CONFIG_ATSTK1004
|
|
||||||
#define CONFIG_ATSTK1000
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
|
|
||||||
* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
|
|
||||||
* PLL frequency.
|
|
||||||
* (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
|
|
||||||
*/
|
|
||||||
#define CONFIG_PLL
|
|
||||||
#define CONFIG_SYS_POWER_MANAGER
|
|
||||||
#define CONFIG_SYS_OSC0_HZ 20000000
|
|
||||||
#define CONFIG_SYS_PLL0_DIV 1
|
|
||||||
#define CONFIG_SYS_PLL0_MUL 7
|
|
||||||
#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
|
|
||||||
/*
|
|
||||||
* Set the CPU running at:
|
|
||||||
* PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CLKDIV_CPU 0
|
|
||||||
/*
|
|
||||||
* Set the HSB running at:
|
|
||||||
* PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CLKDIV_HSB 1
|
|
||||||
/*
|
|
||||||
* Set the PBA running at:
|
|
||||||
* PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CLKDIV_PBA 2
|
|
||||||
/*
|
|
||||||
* Set the PBB running at:
|
|
||||||
* PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CLKDIV_PBB 1
|
|
||||||
|
|
||||||
/* Reserve VM regions for SDRAM and NOR flash */
|
|
||||||
#define CONFIG_SYS_NR_VM_REGIONS 2
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The PLLOPT register controls the PLL like this:
|
|
||||||
* icp = PLLOPT<2>
|
|
||||||
* ivco = PLLOPT<1:0>
|
|
||||||
*
|
|
||||||
* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_PLL0_OPT 0x04
|
|
||||||
|
|
||||||
#define CONFIG_USART_BASE ATMEL_BASE_USART1
|
|
||||||
#define CONFIG_USART_ID 1
|
|
||||||
|
|
||||||
/* User serviceable stuff */
|
|
||||||
#define CONFIG_DOS_PARTITION
|
|
||||||
|
|
||||||
#define CONFIG_CMDLINE_TAG
|
|
||||||
#define CONFIG_SETUP_MEMORY_TAGS
|
|
||||||
#define CONFIG_INITRD_TAG
|
|
||||||
|
|
||||||
#define CONFIG_STACKSIZE (2048)
|
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 115200
|
|
||||||
#define CONFIG_BOOTARGS \
|
|
||||||
"console=ttyS0 root=/dev/mmcblk0p1 rootwait"
|
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND \
|
|
||||||
"mmc rescan; ext2load mmc 0:1 0x10200000 /boot/uImage; bootm"
|
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 1
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration.
|
|
||||||
*/
|
|
||||||
#include <config_cmd_default.h>
|
|
||||||
|
|
||||||
#define CONFIG_CMD_ASKENV
|
|
||||||
#define CONFIG_CMD_EXT2
|
|
||||||
#define CONFIG_CMD_FAT
|
|
||||||
#define CONFIG_CMD_JFFS2
|
|
||||||
#define CONFIG_CMD_MMC
|
|
||||||
|
|
||||||
#undef CONFIG_CMD_FPGA
|
|
||||||
#undef CONFIG_CMD_NFS
|
|
||||||
#undef CONFIG_CMD_SETGETDCR
|
|
||||||
#undef CONFIG_CMD_XIMG
|
|
||||||
|
|
||||||
#define CONFIG_ATMEL_USART
|
|
||||||
#define CONFIG_PORTMUX_PIO
|
|
||||||
#define CONFIG_SYS_HSDRAMC
|
|
||||||
#define CONFIG_MMC
|
|
||||||
#define CONFIG_GENERIC_ATMEL_MCI
|
|
||||||
#define CONFIG_GENERIC_MMC
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DCACHE_LINESZ 32
|
|
||||||
#define CONFIG_SYS_ICACHE_LINESZ 32
|
|
||||||
|
|
||||||
#define CONFIG_NR_DRAM_BANKS 1
|
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_CFI
|
|
||||||
#define CONFIG_FLASH_CFI_DRIVER
|
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_BASE 0x00000000
|
|
||||||
#define CONFIG_SYS_FLASH_SIZE 0x800000
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 135
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x00000000
|
|
||||||
|
|
||||||
#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
|
|
||||||
#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
|
|
||||||
|
|
||||||
#define CONFIG_ENV_IS_IN_FLASH
|
|
||||||
#define CONFIG_ENV_SIZE 65536
|
|
||||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MALLOC_LEN (256*1024)
|
|
||||||
|
|
||||||
/* Allow 2MB for the kernel run-time image */
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000)
|
|
||||||
#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
|
|
||||||
|
|
||||||
/* Other configuration settings that shouldn't have to change all that often */
|
|
||||||
#define CONFIG_SYS_PROMPT "U-Boot> "
|
|
||||||
#define CONFIG_SYS_CBSIZE 256
|
|
||||||
#define CONFIG_SYS_MAXARGS 16
|
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
|
||||||
#define CONFIG_SYS_LONGHELP
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
|
|
||||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
|
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
|
||||||
|
|
@ -1,168 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (C) 2005-2006 Atmel Corporation
|
|
||||||
*
|
|
||||||
* Configuration settings for the ATSTK1002 CPU daughterboard
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
#ifndef __CONFIG_H
|
|
||||||
#define __CONFIG_H
|
|
||||||
|
|
||||||
#include <asm/arch/hardware.h>
|
|
||||||
|
|
||||||
#define CONFIG_AT32AP
|
|
||||||
#define CONFIG_AT32AP7000
|
|
||||||
#define CONFIG_ATSTK1006
|
|
||||||
#define CONFIG_ATSTK1000
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
|
|
||||||
* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
|
|
||||||
* PLL frequency.
|
|
||||||
* (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
|
|
||||||
*/
|
|
||||||
#define CONFIG_PLL
|
|
||||||
#define CONFIG_SYS_POWER_MANAGER
|
|
||||||
#define CONFIG_SYS_OSC0_HZ 20000000
|
|
||||||
#define CONFIG_SYS_PLL0_DIV 1
|
|
||||||
#define CONFIG_SYS_PLL0_MUL 7
|
|
||||||
#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
|
|
||||||
/*
|
|
||||||
* Set the CPU running at:
|
|
||||||
* PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CLKDIV_CPU 0
|
|
||||||
/*
|
|
||||||
* Set the HSB running at:
|
|
||||||
* PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CLKDIV_HSB 1
|
|
||||||
/*
|
|
||||||
* Set the PBA running at:
|
|
||||||
* PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CLKDIV_PBA 2
|
|
||||||
/*
|
|
||||||
* Set the PBB running at:
|
|
||||||
* PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CLKDIV_PBB 1
|
|
||||||
|
|
||||||
/* Reserve VM regions for SDRAM and NOR flash */
|
|
||||||
#define CONFIG_SYS_NR_VM_REGIONS 2
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The PLLOPT register controls the PLL like this:
|
|
||||||
* icp = PLLOPT<2>
|
|
||||||
* ivco = PLLOPT<1:0>
|
|
||||||
*
|
|
||||||
* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_PLL0_OPT 0x04
|
|
||||||
|
|
||||||
#define CONFIG_USART_BASE ATMEL_BASE_USART1
|
|
||||||
#define CONFIG_USART_ID 1
|
|
||||||
|
|
||||||
/* User serviceable stuff */
|
|
||||||
#define CONFIG_DOS_PARTITION
|
|
||||||
|
|
||||||
#define CONFIG_CMDLINE_TAG
|
|
||||||
#define CONFIG_SETUP_MEMORY_TAGS
|
|
||||||
#define CONFIG_INITRD_TAG
|
|
||||||
|
|
||||||
#define CONFIG_STACKSIZE (2048)
|
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 115200
|
|
||||||
#define CONFIG_BOOTARGS \
|
|
||||||
"console=ttyS0 root=mtd3 fbmem=2400k"
|
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND \
|
|
||||||
"fsload; bootm $(fileaddr)"
|
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 1
|
|
||||||
|
|
||||||
/*
|
|
||||||
* After booting the board for the first time, new ethernet addresses
|
|
||||||
* should be generated and assigned to the environment variables
|
|
||||||
* "ethaddr" and "eth1addr". This is normally done during production.
|
|
||||||
*/
|
|
||||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options
|
|
||||||
*/
|
|
||||||
#define CONFIG_BOOTP_SUBNETMASK
|
|
||||||
#define CONFIG_BOOTP_GATEWAY
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration.
|
|
||||||
*/
|
|
||||||
#include <config_cmd_default.h>
|
|
||||||
|
|
||||||
#define CONFIG_CMD_ASKENV
|
|
||||||
#define CONFIG_CMD_DHCP
|
|
||||||
#define CONFIG_CMD_EXT2
|
|
||||||
#define CONFIG_CMD_FAT
|
|
||||||
#define CONFIG_CMD_JFFS2
|
|
||||||
#define CONFIG_CMD_MMC
|
|
||||||
|
|
||||||
#undef CONFIG_CMD_FPGA
|
|
||||||
#undef CONFIG_CMD_SETGETDCR
|
|
||||||
#undef CONFIG_CMD_SOURCE
|
|
||||||
#undef CONFIG_CMD_XIMG
|
|
||||||
|
|
||||||
#define CONFIG_ATMEL_USART
|
|
||||||
#define CONFIG_MACB
|
|
||||||
#define CONFIG_PORTMUX_PIO
|
|
||||||
#define CONFIG_SYS_NR_PIOS 5
|
|
||||||
#define CONFIG_SYS_HSDRAMC
|
|
||||||
#define CONFIG_MMC
|
|
||||||
#define CONFIG_GENERIC_ATMEL_MCI
|
|
||||||
#define CONFIG_GENERIC_MMC
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DCACHE_LINESZ 32
|
|
||||||
#define CONFIG_SYS_ICACHE_LINESZ 32
|
|
||||||
|
|
||||||
#define CONFIG_NR_DRAM_BANKS 1
|
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_CFI
|
|
||||||
#define CONFIG_FLASH_CFI_DRIVER
|
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_BASE 0x00000000
|
|
||||||
#define CONFIG_SYS_FLASH_SIZE 0x800000
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 135
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x00000000
|
|
||||||
|
|
||||||
#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
|
|
||||||
#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
|
|
||||||
|
|
||||||
#define CONFIG_ENV_IS_IN_FLASH
|
|
||||||
#define CONFIG_ENV_SIZE 65536
|
|
||||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MALLOC_LEN (256*1024)
|
|
||||||
|
|
||||||
/* Allow 4MB for the kernel run-time image */
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
|
|
||||||
#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
|
|
||||||
|
|
||||||
/* Other configuration settings that shouldn't have to change all that often */
|
|
||||||
#define CONFIG_SYS_PROMPT "U-Boot> "
|
|
||||||
#define CONFIG_SYS_CBSIZE 256
|
|
||||||
#define CONFIG_SYS_MAXARGS 16
|
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
|
||||||
#define CONFIG_SYS_LONGHELP
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
|
|
||||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x3f00000)
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
|
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
|
||||||
Loading…
Reference in New Issue